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检索条件"主题词=Programmable logic arrays"

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Optically reconfigurable gate array

Optically reconfigurable gate array

引用

Applied Imagery Pattern Recognition Workshop (AIPR)

作者： J. Mumbru G. Panotopoulos D. Psaltis Xin An Gan Zhou Fai Mok Department of Electrical Engineering California Institute of Technology USA Departmend of Electrical Engineering California Institute of Technology USA Holoplex Inc.

Summary form only given, as follows. Reconfigurable processors, like the Field programmable Gate arrays (FPGAs), open new computational paradigms where the processor is able to tailor its internal structure to better implement a given application. A typical FPGA consists of an array of configurable logic blocks and a mesh of interconnections fully programmable by the user to perform a given application. By just changing its internal connectivity, the FPGA can implement a totally different new function. However in most of the applications, the FPGA is configured only once and used as coprocessor to carry out some highly complex or time-consuming computation. The reason for such limitation is the small communication bandwidth between the FPGA chip and the external memory, usually ROM, where the configuration data is stored. The Optically programmable Gate Array (OPGA), an enhanced version of a conventional. FPGA, can overcome this problem. The OPGA utilizes a holographic memory accessed by an array of VCSELs to program its logic. The on-chip logic has been complemented with an array of photodetectors to detect the configuration template recorded in the memory. Combining spatial and shift multiplexing to store the configuration pages in the memory, the OPGA module is very compact and has extremely short configuration time allowing for dynamic reconfiguration. The reconfiguration capability of the OPGA can be applied to solve more efficiently problems in pattern recognition and database searches.

关键词： Optical arrays Field programmable gate arrays programmable logic arrays Holography Reconfigurable logic logic arrays Holographic optical components Coprocessors Bandwidth Read only memory

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Using 3D Printing Technology to Develop Electromyography Signals Based Prosthetic Arm

Using 3D Printing Technology to Develop Electromyography Sig...

引用

Emerging Technologies in Electronics, Computing and Communication (ICETECC), International Conference on

作者： Fahad Ahmed Korai Noor-ul-Ain Mushtaq Syed Amjad Ali Shah Abdul Qadir Ansari Department of Biomedical Engineering Mehran University of Engineering and Technology Jamshoro Pakistan

Electromyography (EMG) which is one of the most common biomedical signals recorded from the human body muscle. It is used to detect the movements in the muscles using an algorithm known as human-machine interfacing (HMI), EMG is widely used in prosthetic arms by amputee individuals. However, both the prosthetic arm and the EMG signal recorders available in the market are costly. As in developing countries, more than 22% of people are below the poverty line and starting price of the commercial prosthetic arm is 500,000/-PKR which is very expensive for the people living in Pakistan who need an affordable prosthetic arm, in this project, the prosthetic arm design was designed and modified on -Computer- aided design (CAD) software and 3D printed using PLA (Polylactic Acid). The prosthetic arm was interfaced with EMG sensor by Arduino microcontroller. It was tested on an individual who was able to generate the movements through muscle contraction, which was detected by an EMG sensor. Therefore, the basic objective of developing a low-cost arm is achieved with the total expense of approx. Rs. 20,000/- (PKR) and the people who lost their limbs can use this 3D Printed prosthetic arm to improve their quality of life.

关键词： Program processors Three-dimensional displays Microcontrollers programmable logic arrays Arms Muscles Three-dimensional printing

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RTD-based compact programmable gates

RTD-based compact programmable gates

引用

International Joint Conference on Neural Networks (IJCNN)

作者： J.M. Quintana M.J. Avedillo H. Pettenghi Instituto de Microelectrónica de Sevilla Centra Nacional de Microelectrónica Seville Spain

This work presents novel and extremely compact implementations of programmable gates on the basis of the multi-threshold threshold gate concept. The circuit consists of resonant tunnelling diodes (RTDs) and heterostructure field effect transistors (HFETs) and its operating principle is based on the controlled quenching of clocked series-connected RTDs. The proposed generic circuit topology is presented and the methodology to design specific programmable gates is introduced. A number of programmable gates are shown and their operation is validated.

关键词： Resonant tunneling devices logic functions programmable logic arrays logic devices Diodes logic design Switches Electronic mail RLC circuits Design methodology

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16kbit 1T1R OxRAM arrays embedded in 28nm FDSOI technology demonstrating low BER, high endurance, and compatibility with core logic transistors

16kbit 1T1R OxRAM arrays embedded in 28nm FDSOI technology d...

引用

IEEE International Memory Workshop (IMW)

作者： L. Grenouillet N. Castellani A. Persico V. Meli S. Martin O. Billoint R. Segaud S. Bernasconi C. Pellissier C. Jahan C. Charpin-Nicolle P. Dezest C. Carabasse P. Besombes S. Ricavy N.-P. Tran A. Magalhaes-Lucas A. Roman C. Boixaderas T. Magis M. Bedjaoui M. Tessaire A. Seignard F. Mazen S. Landis E. Vianello G. Molas F. Gaillard J. Arcamone E. Nowak CEA LETI Univ. Grenoble Alpes Grenoble France

We present for the first time Si-doped HfO2-based OxRAM 16kbit arrays integrated in the BEOL of 28nm FDSOI CMOS, targeting low cost and low power embedded applications. Excellent LRS/HRS raw distributions are reported... 详细信息

We present for the first time Si-doped HfO₂-based OxRAM 16kbit arrays integrated in the BEOL of 28nm FDSOI CMOS, targeting low cost and low power embedded applications. Excellent LRS/HRS raw distributions are reported on 1T-1R 16kbit arrays with zero bit-fail up to 10⁵ cycles, using core logic (GO1) selector transistors. The OxRAM compatibility with GO1 transistors paves the way to arrays with minimum bitcell area of 0.066 μm² at 125μA programming current. We also demonstrate direct correlation between transistor compliance current variability within the 1T-1R array and the LRS distribution. This result indicates that the intrinsic LRS variability is smaller than the measured one. SPICE Monte-Carlo simulations confirm the large compliance current dispersion measured on transistors designed at minimum gate length and show path to improve even further the LRS distribution and hence the OxRAM memory window.

关键词： Monte Carlo methods Nonvolatile memory Current measurement Silicon-on-insulator programmable logic arrays logic gates Programming

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An algorithmic branch and bound method for PLA test pattern generation

An algorithmic branch and bound method for PLA test pattern ...

引用

IEEE International Test Conference

作者： M. Robinson J. Rajski Department of Electrical Engineering McGill University Montreal Canada

A method for PLA (programmable logic-array) test-pattern generation based on a branch-and-bound algorithm that function monotonicity is presented. The algorithm makes irrevocable input assignments first, resulting in the efficient generation of compact test sets. In most cases there is no backtracking. An intelligent branching heuristic is presented. The algorithm handles extended fault models, including cross-point and delay faults. Heuristics which speed up test-set generation and improve test-set compaction are discussed. Results of tests on a wide range of benchmark PLAs are included.< >

关键词： programmable logic arrays Test pattern generators Delay Automatic test pattern generation logic testing Planets Minimization methods AC generators DC generators Heuristic algorithms

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REMO: A RGPS-based requirements modeling process for service oriented Architecture

REMO: A RGPS-based requirements modeling process for service...

引用

International Conference on Networked Computing and Advanced Information Management (NCM)

作者： Bo Hu Keqing He Peng Liang Rong Li State Key Laboratory of Software Engineering Wuhan University of China Wuhan China

Service oriented requirements engineering (SORE) is a main topic in service oriented development, which aims to capture stakeholders' service oriented requirements in a proper specification. In this paper, we proposed a novel process for service oriented requirements modeling. Methodologies in the process enable to establish a layered requirements model from the perspectives of Role, Goal, Process, and Service. Different from other existing requirements engineering processes, our work focuses on modeling requirements from early requirements elicitation phrase. And then, the process can be used in a network and distributed environment to capture stakeholders' need dynamically. In addition, layered requirements modeling process enables explicit requirements modeling from role, goal, process, and service facet. Last but not least, OWL and OWL-S described requirements model contains a wealth of semantic, which enables the model crucial to both human and machine-to-machine communication.

关键词： Brain modeling Books Engines Decision support systems programmable logic arrays

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An energy analysis of polylactic acid (PLA) produced from corn grain and corn stover integrated system

An energy analysis of polylactic acid (PLA) produced from co...

引用

IEEE International Symposium on Electronics and the Environment

作者： Qinghua Guo John C. Crittenden Brook Byers Institute of Sustainable Systems and School of Chemical and Biomolecular Engineering Georgia Institute of Technology Atlanta GA USA Brook Byers Institute of Sustainable Systems and Department of Civil & Environmental Engineering Georgia Institute of Technology Atlanta GA USA

Polylactic acid (PLA) has been identified as one of the most promising biobased plastics for various applications. The nonrenewable energy use of 1 kg PLA produced in an integrated system where both corn grain and corn stover are harvested and used for lactic acid production has been assessed through life cycle assessment. The overall findings are that PLA produced from integrated system does not show advantages compared with current corn starch based system. Feedstock consumption of producing 1 kg PLA is about 1.62 kg corn grain and 0.81 kg corn stover. Nonrenewable energy use associated with PLA resin produced in the integrated system is about 58.9 MJ/kg. In order to facilitate future large scale biobased PLA production, and also reduce its dependence on corn grain which increase food costs, more efforts are needed to focus on choosing appropriate lignocellulosic raw materials and developing more efficient technologies.

关键词： programmable logic arrays Production Plastics Resins Electricity Energy consumption Biomass

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Distributed Key-Insulated group signature scheme

Distributed Key-Insulated group signature scheme

引用

International Conference on Computer Science and Service System (CSSS)

作者： Yan Suo Xiaoyan Xu Yusen Zhang Institute of Command Automation PLA University of Science and Technology Nanjing China

A new Key-Insulated group signature scheme is proposed under standard model. This paper takes advantage of helpers to help update member keys in every time section, meets the forward security and backward security.

关键词： programmable logic arrays Automation Presses Computers Public key

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PLATYPUS: A PLA Test Pattern Generation Tool

PLATYPUS: A PLA Test Pattern Generation Tool

引用

Design Automation Conference

作者： Ruey-Sing Wei A. Sangiovanni-Vincentelli Department of EECS University of California Berkeley CA USA

PLATypus (PLA Test pattern generation and logic simulation tool) is an efficient tool for large PLAs which is interfaced constrained/unconstrained, simple/multiple folding program PLEASURE and the logic minimizer ESPRESSO II-C developed at the University of California at Berkeley. PLATYPUS uses biased random test generation as a quick preprocess followed by a deterministic test generation process to achieve the best balance between efficient run time and test set minimality. The algorithm adopted in the deterministic phase is exact, i.e., it achieves the highest possible test coverage by generating a test for every testable fault. Powerful heuristics are introduced in the area of fault processing order, backend fault simulation, "don't-care" bit fixing, and on-the-fly test compaction to achieve the best performance of PLATYPUS. The deterministic test generation algorithm is based on both complementation and tautology check of a logic cover. Both complementation and tautology check are performed by an advanced method used in the logic minimizer ESPRESSO-II. PLATYPUS supports both folded and unfolded PLAs, and both crosspoint and stuck-at fault models. PLATYPUS can also be used as a logic simulation tool and redundancy identifier. Test pattern generation has been performed by PLATYPUS on a large number of industrial PLAs.

关键词： programmable logic arrays Test pattern generators logic testing Very large scale integration Compaction Redundancy Performance evaluation logic design Feedback System testing

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A methodology for the test of embedded compiled cells

A methodology for the test of embedded compiled cells

引用

Custom Integrated Circuits Conference (CICC)

作者： M.A. Samad T. Butzerin VLSI Technology Inc. San Jose CA USA

The use of compilers for structured cells such as RAMs, ROMs, multipliers and PLAs (programmable logic arrays) has become widespread in the design of application-specific integrated circuits (ASICs). The authors present a methodology for testing circuits made from these compiled cells. The key elements of this methodology are the vector compilers that generate test suites for the compiled cells and an isolation strategy that allows these test suites to be applied to embedded functional blocks.< >

关键词： Circuit testing Read only memory programmable logic arrays Application specific integrated circuits Circuit faults Very large scale integration Integrated circuit technology Timing Shape Program processors

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