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检索条件"主题词=Programmable logic arrays"

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Autocorrelation techniques for multi-bit decoder PLAs

Autocorrelation techniques for multi-bit decoder PLAs

引用

International Symposium on Multiple-Valued logic

作者： R. Tomczuk D.M. Miller VLSI Design and Test Group Department of Computer Science University of Victoria Victoria BC Canada

The area required by a PLA can be reduced using multibit rather than single-bit input decoders. In such a PLA, the input variables are partitioned into disjoint subsets, each of which is used as the input to a decoder. The output of the decoders, instead of the input signals and their complements, are used in the core of the PLA. The problem of assigned pairs of input variables to two-bit decoders is addressed. Variable pair selection is based on the total autocorrelation of a system of Boolean functions. Preliminary results on the use of autocorrelation coefficients in the assignment of triples of variables to decoders are also presented.< >

关键词： Autocorrelation Decoding programmable logic arrays Input variables Boolean functions Very large scale integration Testing Computer science Propagation delay Minimization methods

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Design of the DIII-D top level power supply control system for an eighth neutral beam ion source

Design of the DIII-D top level power supply control system f...

引用

IEEE/NPSS Symposium on Fusion Engineering

作者： G.L. Campbell K.L. Holtrop General Atomics San Diego CA USA

The DIII-D project will be commissioning an eighth neutral beam ion source during CY09. Part of this effort includes returning one of the neutral beam power supplies (NBPS) to full operation. For the past 10 years, the high voltage DC portion of this system had been used to power gyrotrons in the DIII-D electron cyclotron heating system. The idle filament, magnet, arc and suppressor power supplies will be refurbished using their existing technology. The modulator/regulator for the accelerator (plasma) grid voltage is being upgraded with new controls. Interlocking and coordination of the individual supplies within the NBPS is performed by the local control station (LCS). The new design of the LCS will be presented. The current implementation of the LCS is characterized by discrete relay and CMOS logic and the use of CAMAC interfaces to the neutral beam control and data acquisition systems. These older and difficult to maintain components will be replaced with an Ethernet connected programmable logic controller and a field programmable gate array design for timing functions. Operator interfaces will change from hardwired switches and panels to graphical user interfaces on multiple screens with the capability for remote monitoring and operation. Due to schedule constraints, some of the more reliable solid state circuits in the LCS will not be immediately replaced, but an easy migration path is mapped that will cost minimal downtime once the eighth source is in operation. This project is expected to result in a viable prototype for upgrading each LCS in the other seven neutral beam power systems at DIII-D.

关键词： Power supplies Control systems Ion beams Ion sources Plasma accelerators programmable logic arrays Voltage Gyrotrons Electrons Cyclotrons

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A MPPT Method Based on the Approximation of a PVM Model using Fractional Polynomials

A MPPT Method Based on the Approximation of a PVM Model usin...

引用

Annual IEEE Conference on Power Electronics Specialists (PESC)

作者： Eduardo I. Ortiz-Rivera Department of Electrical and Computer Engineering University of Puerto Rico Mayaguez Puerto Rico

This paper presents a non-traditional method for the approximation of the photovoltaic module, PVM, exponential model using fractional polynomials where the shape, boundary conditions and performance of the original system are satisfied. The proposed Maximum Power Point Method uses these fractional polynomials to obtain analytically the optimal solutions for the maximum power, Pmax for the PVM operation, optimal voltage, Vop, and optimal current, lop. Also, if the characteristics of the PVM array are known the method can be program in an Arithmetic logic Unit, ALU, and estimate the maximum power measuring the open circuit voltage, V x and short circuit current, I x . Examples and simulations to validate the proposed MPPT are given in the paper using data sheet for different types of PVM's. Finally, the proposed method is excellent to approximate the PVM exponential model and provide a different way to approximate exponential functions that are not possible to solve using differential calculus.

关键词： Polynomials Power system modeling Voltage programmable logic arrays Photovoltaic systems Solar power generation Shape Boundary conditions Arithmetic logic arrays

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A 13,000 transistor NMOS microprocessor

A 13,000 transistor NMOS microprocessor

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IEEE International Conference on Solid-State Circuits (ISSCC)

作者： R. Olsen D. Dobberpuhl Digital Equipment Corporation Hudson MA USA

This report will cover a 16b NMOS microprocessor which combines a minicomputer instruction set with a micro-processor bus.

关键词： MOS devices Microprocessors programmable logic arrays Electrical equipment industry Large scale integration Timing logic testing Integrated circuit interconnections Registers Driver circuits

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Throughput optimization by pipeline alignment of a Self Synchronous FPGA

Throughput optimization by pipeline alignment of a Self Sync...

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IEEE International Conference on Field-programmable Technology (FPT)

作者： Benjamin Devlin Toru Nakura Makoto Ikeda Kunihiro Asada Department of Electronic Engineering University of Tokyo Bunkyo Tokyo Japan VLSI Design and Education Center University of Tokyo Japan Tokyo Daigaku Bunkyo-ku Tokyo JP

We report on the throughput optimization of a self synchronous FPGA (SSFPGA) using benchmark circuits. We find that using a dual pipeline architecture we are able to convert synchronous designs from verilog onto our SSFPGA, and by using pipeline alignment techniques to match pipeline depth we can perform at maximum throughput. We demonstrate 0 to 56.1 times throughput improvement with our pipeline alignment techniques. The pipeline alignment is carried out within the number of logic elements in the array and pipeline buffers in the switching matrix.

关键词： Throughput Field programmable gate arrays Pipeline processing Circuits programmable logic arrays Random access memory Wire Design optimization logic arrays Switches

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MemMap-pd: performance driven technology mapping algorithm for FPGAs with embedded memory arrays

MemMap-pd: performance driven technology mapping algorithm f...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： A. Manoj Kumar B. Jayaram R. Manimegalai V. Kamakoti Indian Institute of Technology Madras Chennai India

Summary form only given. Modern day field programmable gate arrays (FPGA) include in addition to look-up tables, reasonably big configurable embedded memory blocks (EMB) to cater to the on-chip memory requirements of systems/applications mapped on them. While mapping applications on to such FPGAs, some of the EMBs may be left unused. We present a methodology to utilize such unused EMBs as large look-up tables to map multioutput combinational subcircuits of the application, with depth minimization as the main objective along with area minimization in terms of the number of LUTs used. Depth minimization is an important goal while mapping performance driven circuits. Experimental results show that our proposed methodology, when employed on popular benchmark circuits, leads to up to 14% reduction in depth when compared with the DAG-map algorithm, along with comparable reduction in area.

关键词： Field programmable gate arrays Random access memory Table lookup programmable logic arrays System-on-a-chip Circuit synthesis Minimization methods Read-write memory Lattices logic arrays

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Using an Electric programmable Analog Array for IEEE 1451 compliant Transducer Applications

Using an Electric Programmable Analog Array for IEEE 1451 co...

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Ph.D. Research in Microelectronics and Electronics (PRIME)

作者： O. Reimer J. Kampe Faculty of Electrical Engineering and Information Technology Institute of Electronic Circuits and Systems Technical University Ilmenau Ilmenau Germany

This paper introduces a programmable analog circuit and its application as a universal interface-module for transducers (sensors and actuators). As a basis the recently introduced smart transducer interface standards ... 详细信息

关键词： Transducers Protocols programmable logic arrays Sensor arrays Intelligent sensors Plugs Information technology Electronic circuits Analog circuits Actuators

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Finding composition trees for multiple-valued functions

Finding composition trees for multiple-valued functions

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International Symposium on Multiple-Valued logic

作者： E.V. Dubrova J.C. Muzio B. von Stengel VLSI Design and Test Group University of Victoria Victoria BC Canada Theoretical Computer Science ETH Zürich Zurich Switzerland

The composition tree of a given function, when it exists, provides a representation of the function revealing all possible disjunctive decompositions, thereby suggesting a realization of the function at a minimal cost. Previously and independently, the authors had studied the class of multiple-valued functions that are fully sensitive to their variables. These functions are useful for test generation purposes, and almost all m-valued n-variable functions belong to this class as n increases. All functions in this class have composition trees. This paper presents a recursive algorithm for generating the composition tree for any function in this class. The construction proceeds top-down and makes immediate use of any encountered decomposition, which reduces the (in general exponential) computation time.

关键词： programmable logic arrays Phased arrays Cost function Testing logic devices logic circuits Very large scale integration Field programmable gate arrays Councils Microelectronics

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PLATYPUS: A PLA Test Pattern Generation Tool

PLATYPUS: A PLA Test Pattern Generation Tool

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Design Automation Conference

作者： Ruey-Sing Wei A. Sangiovanni-Vincentelli Department of EECS University of California Berkeley CA USA

PLATypus (PLA Test pattern generation and logic simulation tool) is an efficient tool for large PLAs which is interfaced constrained/unconstrained, simple/multiple folding program PLEASURE and the logic minimizer ESPRESSO II-C developed at the University of California at Berkeley. PLATYPUS uses biased random test generation as a quick preprocess followed by a deterministic test generation process to achieve the best balance between efficient run time and test set minimality. The algorithm adopted in the deterministic phase is exact, i.e., it achieves the highest possible test coverage by generating a test for every testable fault. Powerful heuristics are introduced in the area of fault processing order, backend fault simulation, "don't-care" bit fixing, and on-the-fly test compaction to achieve the best performance of PLATYPUS. The deterministic test generation algorithm is based on both complementation and tautology check of a logic cover. Both complementation and tautology check are performed by an advanced method used in the logic minimizer ESPRESSO-II. PLATYPUS supports both folded and unfolded PLAs, and both crosspoint and stuck-at fault models. PLATYPUS can also be used as a logic simulation tool and redundancy identifier. Test pattern generation has been performed by PLATYPUS on a large number of industrial PLAs.

关键词： programmable logic arrays Test pattern generators logic testing Very large scale integration Compaction Redundancy Performance evaluation logic design Feedback System testing

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REMO: A RGPS-based requirements modeling process for service oriented Architecture

REMO: A RGPS-based requirements modeling process for service...

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International Conference on Networked Computing and Advanced Information Management (NCM)

作者： Bo Hu Keqing He Peng Liang Rong Li State Key Laboratory of Software Engineering Wuhan University of China Wuhan China

Service oriented requirements engineering (SORE) is a main topic in service oriented development, which aims to capture stakeholders' service oriented requirements in a proper specification. In this paper, we proposed a novel process for service oriented requirements modeling. Methodologies in the process enable to establish a layered requirements model from the perspectives of Role, Goal, Process, and Service. Different from other existing requirements engineering processes, our work focuses on modeling requirements from early requirements elicitation phrase. And then, the process can be used in a network and distributed environment to capture stakeholders' need dynamically. In addition, layered requirements modeling process enables explicit requirements modeling from role, goal, process, and service facet. Last but not least, OWL and OWL-S described requirements model contains a wealth of semantic, which enables the model crucial to both human and machine-to-machine communication.

关键词： Brain modeling Books Engines Decision support systems programmable logic arrays

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