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检索条件"主题词=Programmable logic arrays"

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Pleasure: A Computer Program for Simple/Multiple Constrained/Unconstrained Folding of programmable logic arrays 83

Pleasure: A Computer Program for Simple/Multiple Constrained...

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Design Automation Conference

作者： G. De Micheli A. Sangiovanni-Vincentelli Department of EECS University of California at Berkeley Berkeley CA Department of EECS University of California Berkeley Berkeley CA USA

ISBN: (纸本)9780818600265

programmable logic arrays are important building blocks of VLSI circuits and systems. We address the problem of optimizing the silicon area and the performances of large logic arrays. In particular we describe a general method for compacting a logic array defined as multiple row and column folding and we address the problem of interconnecting a PLA to the outside circuitry. We define a constrained optimization problem to achieve minimal silicon area occupation with constrained positions of electrical inputs and outputs. We present a new computer program, PLEASURE, which implements several algorithms for multiple and/or constrained PLA folding.

关键词： programmable logic arrays logic arrays Very large scale integration logic circuits Silicon logic design Circuits and systems Constraint optimization Equations Minimization

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Learning VLSI design using programmable logic arrays

Learning VLSI design using programmable logic arrays

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Frontiers in Education (FIE) Conference

作者： E.I. Boemo J.M. Meneses E.T.S.I. Telecommunicatión

The authors describe technical aspects, organization details, and results of an experimental undergraduate laboratory based on field programmable gate arrays at the School of Telecommunication of Madrid, Spain. The target of the course has been to introduce concepts of ASIC (application-specific integrated circuit) design methodology such as hierarchy, modularity, simulation, and testability, using a low alternative and a design-oriented, hands-on learning approach.< >

关键词： programmable logic arrays Very large scale integration logic design Field programmable gate arrays Circuit testing Laboratories Design automation Design for testability Application specific integrated circuits Software design

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Test generation and logic/fault simulation of programmable logic arrays: optimized partitioning techniques for parallel processing

Test generation and logic/fault simulation of programmable l...

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Midwest Symposium on Circuits and Systems (MWSCAS)

作者： A. Cruz D. Sarma Department of Mathematics & Computer Science Universidad de Puerto Rico Puerto Rico Department of Mathematics Rutgers University Cherry Hill NJ USA

Much research has been done to increase the efficiency for PLA test generation algorithms. However, the overall gains achieved with the increased efficiency do not keep pace with the increase in PLA size, e.g. computation times are still excessive. For large PLAs the time needed to generate test vectors and to verify correctness of actual implementation on uniprocessor systems is quite prohibitive. However, the recent availability of multiprocessors makes possible great improvements in potential performance for test generation as well as logic/fault simulation. Research using multiprocessors for PLA testing and simulation is still in the very early stages of development.

关键词： programmable logic arrays logic testing Upper bound Multitasking Computational modeling Mathematics Parallel processing Computer science Partitioning algorithms System testing

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Multiple constrained folding of programmable logic arrays by simulated annealing

Multiple constrained folding of programmable logic arrays by...

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Mediterranean Electrotechnical Conference (MELECON)

作者： J. Ballesteros J.M. Sanchez Departmento Informática Esc. University de Extremadura Universitat Poliltècnica de Catalunya Caceres Spain Departmento Informática y Automática Faculty Fisicas Universite Complutense de Madrid Madrid Spain

The PLA (programmable logic array) topological optimization problem is dealt with using folding techniques. Multiple unconstrained column folding is considered and this problem is solved using the simulated annealing algorithm. This algorithm is then extended to handle several types of constraints. Multiple constrained folding problems are solved using bipartite graphs. This allows the system to move only into a set of valid solutions. Comments are made concerning the experimental results obtained in the algorithm execution.< >

关键词： programmable logic arrays Simulated annealing Input variables Cost function Bipartite graph logic design Very large scale integration Algorithm design and analysis Delay lines Boolean functions

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Field programmable logic arrays Implementation of Scene-Based Nonuniformity Correction Algorithm

Field Programmable Logic Arrays Implementation of Scene-Base...

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International Conf on Electrical and Electronic Engineering (ICEEE)

作者： Josphat Chege Njuguna Emre Alabay Anil Çelebi Electronics and Communication Engineering Kocaeli University Kocaeli Turkey

ISBN: (纸本)9781665440714;9781665411615

In this paper, the implementation of scene-based nonuniformity correction (SBNUC) algorithm is presented based on field programmable logic arrays (FPGA) for infrared focal plane arrays (IRFPA). An efficient hardware architecture for the proposed algorithm is presented. The architecture is modeled using C++ in the High-level Synthesis (HLS) tool. Furthermore, it is implemented on an FPGA device fabricated at a 16nm technology node. According to experimental results, low resource utilization, low power consumption, and a maximum frequency of 300MHz are achieved. The simulation and MATLAB results are compared to test the accuracy in which there are close similarities.

关键词： Digital signal processors Signal processing algorithms programmable logic arrays Tools Streaming media Hardware Real-time systems

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A method for testing partially programmable logic arrays in CPLDs

A method for testing partially programmable logic arrays in ...

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International Automatic Testing Conference, AUTOTESTCON

作者： J. Bailey C. Stroud N. Vocke N. Lau W. Orso C. Tran Department of Electrical Engineering University of Kentucky Lexington KY USA Cypress Semiconductor San Jose CA USA

We describe a method for developing a minimal set of four test configurations with associated minimum sets of test patterns that completely tests reprogrammable programmable logic arrays (PLAs) with partially programmable OR-planes typically found in Complex programmable logic Devices (CPLDs). The resultant set of test configurations and vectors detect all single and multiple stuck-at faults (including line and transistor faults) as well as all bridging faults without requiring hardware modifications in the PLA. Previous methods for testing reprogrammable PLAs have dealt only with fully programmable OR-planes.

关键词： programmable logic arrays logic testing Circuit faults Circuit testing logic devices logic programming Fault detection Hardware programmable logic devices EPROM

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Parallel algorithms for minimizing multiple-valued programmable logic arrays

Parallel algorithms for minimizing multiple-valued programma...

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International Symposium on Multiple-Valued logic

作者： P.P. Tirumalai V.G. Vadakkencherry Hewlett Packard Laboratories Palo Alto CA USA California Design Center MS 53U/57 Hewlett Packard Company Santa Clara CA USA

Two versions of a minimization algorithm for multiple-valued programmable logic arrays for shared and distributed memory multiprocessor systems are presented. Both algorithms exploit the considerable parallelism available in the minimization problem. Discussed are communication, synchronization, and load balancing issues under the two machine models. Limited access and the cost of the required computation prevented running of the two parallel algorithms on the actual machines; however, it was possible to run parallel algorithms for a different, but very similar, problem that required less computation. These results indicate that excellent speedups, in some cases superlinear (i.e, more than the number of processors), can be obtained from parallel implementations of this logic minimization algorithm.< >

关键词： programmable logic arrays Parallel algorithms Minimization methods logic devices Costs programmable logic devices CMOS logic circuits Concurrent computing logic circuits logic design

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Design aids and test results for laser-programmable logic arrays

Design aids and test results for laser-programmable logic ar...

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IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： D.L. Allen R. Goldenberg MIT Lincoln Laboratories Lexington MA USA

The time required to customized a logic array circuit can be reduced to minutes by the use of laser programming without the access and resistance limitations of electrically programmable devices. A restructable logic array (RLA) that can be completely tested before packaging and can be fabricated in a standard CMOS process has been developed. Its key element is a connective laser link device. Circuits of up to 1200 gate equivalents have been restructured, and a base array of 4000 raw gate equivalents is in fabrication. A chip architecture, associated testing, and electrical design features, as well as their use in custom circuits are described.< >

关键词： logic testing logic arrays Optical design logic design Optical arrays Circuit testing logic programming programmable logic arrays logic devices CMOS logic circuits

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A new low overhead design for testability of programmable logic arrays

A new low overhead design for testability of programmable lo...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： B.D. Liu J.J. Sheu Department of Electrical Engineering National Cheng Kung University Tainan Taiwan

A new design to reduce the overhead required for fully testable programmable logic arrays (PLAs) is proposed. This design exploits the fact that product lines in a PLA can be rearranged and grouped into few partitions. Then, some extra outputs are added, one per partition, to make the whole PLA testable. Compared with the previous PLA design-for-testability techniques, the algorithm presented is very feasible, and its implementation is straightforward. Furthermore, this algorithm significantly lowers overhead and provides substantially higher fault coverage than some existing schemes.< >

关键词： programmable logic arrays Design for testability logic design logic testing Circuit testing Built-in self-test Controllability Design automation Automatic testing Degradation

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The structure of complete test sets for programmable logic arrays

The structure of complete test sets for programmable logic a...

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European Test Conference

作者： E.I. Goldberg Y.A. Novikov Belarusian Academy of Sciences Minsk Belarus

A new approach to complete testing of a PLA without any auxiliary facilities is presented. PLA testability is provided by the exact minimization of the PLA in the number of product lines. A theorem about the structure of a complete test set detecting all testable single and multiple crosspoint faults in such a minimal PLA is presented. It formulates the three conditions to which the complete test set satisfies. A technique for constructing complete test sets is discussed.< >

关键词： programmable logic arrays logic testing Fault detection Very large scale integration Cybernetics logic design Degradation Decoding

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