检索结果-内蒙古大学图书馆

Year 2000: Where do you stand?

CONTROL ENGINEERING 1998年第2期45卷 65-+页

作者： Jacobsen, EC TAVA Technol ACS Operat W Chester PA 19380 USA

The Year 2000 bug (Y2K or millennium bug) is touted as modern automation's biggest glitch, and the people most proactively addressing the issue are those associated with the upper-level business systems. Unfortunately, many people do not associate software programming with plant-floor control systems. The process of performing a detailed compliance assessment of plant-floor software and addressing the problem if there are any can be organized into: assessment (project setup and system inventory);analysis (suspect and impact), conversion planning (project planning);and implementation (project execution and testing/commissioning).

关键词： software for control year 2000 industrial personal computers programmable logic controllers

来源：评论

学校读者我要写书评

暂无评论

Decision Support System for Cyber Attack Diagnosis in Smart Water Networks

引用

IFAC-PapersOnLine 2019年第34期51卷 329-334页

作者： Quiñones-Grueiro, Marcos Prieto-Moreno, Alberto Verde, Cristina Llanes-Santiago, Orestes Department of Automation and Computing CujaeHavana Cuba Instituto de Ingeniería-UNAM Coyoacan04510 Mexico

This paper presents the design of a Decision Support System (DSS) for cyber attack diagnosis in Smart Water Networks. Cyber physical systems (CPS) integrate physical assets with embedded systems. Smart water networks are CPS formed by the distribution system of pipes together with sensors, actuators, programmable logic controllers (PLCs) and supervisory control and data acquisition (SCADA) system. The proposed strategy combines three signal processing tools: Principal Component Analysis, the Adaptive Exponential Weighted Moving Average Chart and the Reconstruction-based Contribution method. The proposal is tested with the data published in the BATtle of the Attack Detection ALgorithms (BATADAL) competition (http://***). The results show that the proposed DSS allows the detection of all the attacks from the test data set 3 with a satisfactory performance by using only data from the normal behavior (data set 1). The proposed DSS can also successfully identify the area of the network and the physical component(s) under attack for different scenarios (first three attacks). © 2019

关键词： Monitoring Computer crime Crime Cyber Physical System Data acquisition Decision support systems Distributed database systems Embedded systems Network security programmable logic controllers Signal processing Statistical tests Water distribution systems Cyber attacks Cyber physical systems (CPS) Decision support system (dss) Distribution systems Exponential weighted moving average Physical components Spatially distributed system Supervisory control and dataacquisition systems (SCADA)

来源：评论

学校读者我要写书评

暂无评论

Data-Driven Approach for Feature Drift Detection in Embedded Electronic Devices ⁎

引用

IFAC-PapersOnLine 2018年第24期51卷 1024-1029页

作者： Djedidi, Oussama Djeziri, Mohand A. M'Sirdi, Nacer K. Aix Marseille University Université de Toulon CNRS LIS SASV Marseille France

This paper is a part of a project aiming to develop supervisor and monitoring devices for embedded systems in airplanes and vehicles. It focuses on the reliability of these systems and establishes a monitoring framework to detect drifts and faults in the behavior of the heterogeneous central processing units (CPU) and graphics processing units (GPU) chips powering them. In this work, we use a previously developed incremental model of these chips and associate it with a fault detection algorithm. Estimations from the model constitute inputs to the diagnosis module. The latter generates alarms in the presence of faults or drifts in the characteristics and features of the System-on-Chip (SoC). The obtained results validate the proposed monitoring algorithm and demonstrate the effectiveness of the fault detection algorithm. © 2018

关键词： Monitoring Computer graphics Embedded systems Fault detection Graphics processing unit Identification (control systems) Microprocessor chips Models Program processors programmable logic controllers Signal detection System on chip Analytical redundancy Embedded electronic devices Fault detection algorithm Graphics Processing Unit (GPU) Incremental modeling Monitoring algorithms Monitoring frameworks System on chips (SoC)

来源：评论

学校读者我要写书评

暂无评论

Proposal discharging station compatible with CHAdeMO automotive standard

引用

IFAC-PapersOnLine 2018年第6期51卷 277-282页

作者： Mikolajek, Martin Vala, David Freiedrischkova, Kristyna Koziorek, Jiri Horak, Bohumil VSB TU Ostrava FEI Department of Cybernetics and Biomedical Engineering 17 Listopadu 15 Ostrava70833 Czech Republic

The paper is about proposal battery discharging station for automotive using by CHAdeMO standard. The article talks about this and other types of electric batteries sockets for electric cars. The main aim of this paper is talking about main points for create discharging station by CHAdeMO standard. Each communication standard has some advantages and disadvantages. This article contain using recharger socket with Can bus communication standard. First parts of this paper talks about proposal of discharging station. Continuing chapters are about realized and testing discharging automotive battery station. © 2018

关键词： Battery management systems Electric automobiles Electric connectors programmable logic controllers Secondary batteries Automotive battery Automotive standards Battery Management Can bus communications Communication standards discharging station Electric cars Electric connections

来源：评论

学校读者我要写书评

暂无评论

Automatic verification stimulus generation for interface protocols modeled with non-deterministic extended FSM

引用

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2009年第5期17卷 723-727页

作者： Shih, Che-Hua Huang, Juinn-Dar Jou, Jing-Yang Department of Electronics Engineering National Chiao Tung University 300x Taiwan

Verifying if an integrated component is compliant with certain interface protocol is a vital issue in component-based system-on-a-chip (SoC) designs. For simulation-based verification, generating massive constrained simulation stimuli is becoming crucial to achieve a high verification quality. To further improve the quality, stimulus biasing techniques are often used to guide the simulation to hit design corners. In this paper, we model the interface protocol with the non-deterministic extended finite-state machine (NEFSM), and then propose an automatic stimulus generation approach based on it. This approach is capable of providing numerous biasing strategies. Experiment results demonstrate the high controllability and efficiency of our stimulus generation scheme. © 2006 IEEE.

关键词： programmable logic controllers

来源：评论

学校读者我要写书评

暂无评论

DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge

引用

IEEE Journal of Solid-State Circuits 2023年第1期58卷 203-215页

作者： Houshmand, Pouya Sarda, Giuseppe M. Jain, Vikram Ueyoshi, Kodai Papistas, Ioannis A. Shi, Man Zheng, Qilin Bhattacharjee, Debjyoti Mallik, Arindam Debacker, Peter Verkest, Diederik Verhelst, Marian ESAT-MICAS KU Leuven Leuven3000 Belgium KU Leuven Leuven3000 Belgium Imec Leuven3001 Belgium

DIgital-ANAlog (DIANA), a heterogeneous multi-core accelerator, combines a reduced instruction set computer - five (RISC-V) host processor with an analog in-memory computing (AIMC) artificial intelligence (AI) accelerator and a digital reconfigurable deep neural network (DNN) accelerator in a single system-on-chip (SoC) to support a wide variety of neural network (NN) workloads. AIMC cores can bring extreme computational parallelism and efficiency at the expense of accuracy and dataflow flexibility. Digital AI co-processors, on the other hand, guarantee accuracy through deterministic compute, but cannot achieve the same computational density and efficiency. DIANA exploits this fundamental tradeoff by integrating both types of cores in a shared and optimized memory system, to enable seamless execution of the workloads on the parallel cores. The system's performance benefits further from pipelined parallel execution across both accelerator cores and enhanced AIMC spatial unrolling techniques, leading to drastically reduced execution latency and reduced memory footprints. The design has been implemented in a 22-nm technology and achieves peak efficiencies of 600 TOP/s/W for the AIMC core (I/W/O: 7/1.5/6 bit) and 14 TOP/s/W (I/W/O: 8/8/8 bit) for the digital accelerator, respectively. End-to-end performance evaluation of CIFAR-10 and ImageNet classification workloads is carried out on the chip, reporting 7.02 and 5.56 TOP/s/W, respectively, at the system level. © 2022 IEEE.

关键词： programmable logic controllers

来源：评论

学校读者我要写书评

暂无评论

Matching Discrete Signals for Hardware-in-the-Loop-Testing of PLCs

引用

IFAC-PapersOnLine 2018年第10期51卷 229-234页

作者： Thönnessen, David Rakel, Stefan Reinker, Niklas Kowalewski, Stefan Informatik 11 – Embedded Software RWTH Aachen University Germany

Executing Hardware-in-the-Loop (HiL) tests means to compare the actual behavior of a System Under Test (SUT) against a specification of its desired behavior, specified by the tester. The behavior of the SUT is available in form of time- and value-discrete signals coming from the SUT's I/O-modules. The HiL simulator compares these signals to reference signals, defined by the specification. Our approach performs this comparison by matching signal pairs, i.e. matching the actual and reference signal. We apply tolerances in order to allow the actual signal to deviate from the reference without causing the test to fail. © 2016

关键词： Embedded systems Applications Hardware Hardware in the loop simulation Manufacture Process control programmable logic controllers Signal processing Specifications Synthetic apertures Testing Verification Discrete signal Hardware in the loops Hardware in the loop testing Reference signals System under test Validation

来源：评论

学校读者我要写书评

暂无评论

Construction and Verification of PLC LD Programs by the LTL Specification

引用

AUTOMATIC CONTROL AND COMPUTER SCIENCES 2014年第7期48卷 424-436页

作者： Kuzmin, E. V. Sokolov, V. A. Ryabukhin, D. A. Demidov Yaroslavl State Univ Ul Sovetskaya 14 Yaroslavl 150000 Russia

An approach to the construction and verification of LD programs of programmable logic controllers (PLC) for discrete problems is proposed. The specification of the program behavior is per-formed using the linear temporal logic language (LTL). Programming is performed using the Ladder Diagram (LD) language by the LTL specification. The correctness analysis of the LTL specification is performed using the Cadence SMV symbolic model-checking tool. An approach to programming and verifying the PLC LD programs is shown using an example. The LD program, its LTL specification, and an SMV model are given for a discrete problem. This article is aimed at the description of an approach to PLC programming that will provide the correctness analysis of PLC LD programs using the model-checking method. Therefore, the variation in each programmable variable is described using a pair of LTL formulas. The first LTL formula describes situations in which the corresponding variable increases and the second LTL formula specifies conditions leading to a decrease in the variable. LTL formulas, which are considered to specify the behavior of variables, are constructive in the sense that the PLC program corresponding to the temporal properties expressed by these formulas is constructed by them. Thus, PLC programming is reduced to the construction of the LTL specification for the behavior of each programmed variable. In addition, the SMV model of the PLC LD program is constructed by the LTL specification. Then, the SMV model is analyzed for correctness (relative to additional conventional general-programming LTL properties) by the Cadence SMV symbolic model-checking tool.

关键词： programmable logic controllers software engineering specification and verification of PLC programs Ladder Diagram

来源：评论

学校读者我要写书评

暂无评论

programmable logic Controller for Embedded Implementation of Input-Constrained Systems

引用

IFAC-PapersOnLine 2017年第1期50卷 14412-14417页

作者： Levenson, Richard M. Nelson, Zachary E. Adegbege, Ambrose A. Department of Electrical and Computer Engineering The College of New Jersey EwingNJ08628-0718 United States Department of Electrical and Computer Engineering The Johns Hopkins University BaltimoreMD21218 United States

programmable logic controllers (PLCs) have the benefit of being able to withstand a variety of environments while maintaining high reliability compared to computers and other controllers. Traditionally, PLCs have been used for simple ON-OFF control schemes or for proportional-integral-derivative (PID) control. However, recent developments in technology have allowed even low-cost PLCs to implement more advanced and efficient algorithms. This paper investigates a PLC implementation of the specialized Projected Gauss-Seidel (PGS) algorithm. The PGS algorithm is able to quickly and efficiently solve both symmetric and asymmetric mathematical programming problems. The algorithm can be further utilized to solve more complicated problems such as model predictive control (MPC). The focus of this paper is to solve a general constrained optimization problem on a PLC and to expand the capability to solve a MPC example. The Directlogic Do-More PLC is exploited both for computational efficiency and for memory utilization. © 2017

关键词： controllers Computation theory Computational efficiency Computer circuits Constrained optimization Embedded systems Mathematical programming Model predictive control Predictive control systems Problem solving programmable logic controllers Programmed control systems Proportional control systems Two term control systems Embedded implementation Gauss Seidel General constrained optimization High reliability Input constrained systems Mathematical programming problem Memory utilization Proportional integral derivative control

来源：评论

学校读者我要写书评

暂无评论

Hardware Mapping Strategies of PLC Programs in FPGAs

引用

IFAC-PapersOnLine 2018年第6期51卷 131-137页

作者： Milik, Adam Hrynkiewicz, Edward Institute of Electronics Silesian University of Technology of Gliwice Poland

The automatic implementation of fast operating PLCs with massive parallel hardware processing is expected by wide range of designers not familiar with details of computation algorithms design in hardware. The paper presents an approach to implement the fixed point arithmetic computations of control programs with ability of computation resource sharing. The method is based on developed intermediate graph representation for PLC programming languages. The graph representation of a PLC program allows to reveal and to implement parallel computations. Presented methods are dedicated for FPGA architectures and enables utilization of pipelined processing. It is based on multiple stages scheduling shown in detail. Presented methods are intended to improve the efficiency of computation resource utilization of the direct mapping method. The paper is concluded with experiments results that compare achieved performance and resource requirements. © 2018

关键词： Field programmable gate arrays (FPGA) Fixed point arithmetic Hardware Mapping Pipe linings Pipeline processing systems programmable logic controllers Scheduling Automatic implementation Computation algorithm Computation resources Graph representation Parallel Computation Pipelined processing Resource requirements Resource sharing

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：