The current Internet struggles to meet the deterministic transmission requirements in terms of end-to-end delay. Time-sensitive networking (TSN) provides a solution by offering deterministic forwarding services for cr...
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The current Internet struggles to meet the deterministic transmission requirements in terms of end-to-end delay. Time-sensitive networking (TSN) provides a solution by offering deterministic forwarding services for critical flows, ensuring strict latency requirements. However, the costs and complexity of hardware associated with TSN increases the barriers for researchers to build prototype for validating newly proposed queue scheduling algorithms. To address this dilemma, software-based simulation platforms are widely used for reduction of simulation expenses. However, these platforms cannot flexibly simulate various queue scheduling algorithms. Although existing programmable packet scheduling methods can adapt to TSN queue scheduling algorithms for common hardware base, they cannot be directly applied to software-based TSN simulation platforms. In response, we propose a novel lightweight software-defined packetscheduling primitive-first-in-pick-out (FIPO), based on the programmable switch behavior-model-version-2 (BMV2). FIPO is capable of expressing customized queue scheduling algorithms to support current TSN algorithms and can be flexibly extended to future algorithms. Particularly, FIPO consists only of multipriority queues and eligible time comparator to implement TSN queue scheduling with minimal computational and management overhead. We also propose a fine-grained logical queue-based flow queue mechanism to enhance FIPO. Finally, a lightweight prototype system for the FIPO is established, incorporating four customized deterministic scheduling algorithms. Extensive experimental results show that FIPO can quickly implement customized queue scheduling algorithms and simulate network conditions that closely resemble real environments. It also demonstrates increased implementation flexibility, achieving millisecond-level configuration times with only a moderate increase in CPU utilization (less than 10%).
With the rapid development of network devices and increasingly high CPU workloads, packetscheduling will have to be offloaded to hardware. programmable packet scheduling allows scheduling algorithms to be programmed ...
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With the rapid development of network devices and increasingly high CPU workloads, packetscheduling will have to be offloaded to hardware. programmable packet scheduling allows scheduling algorithms to be programmed into network devices without modifying the hardware. It not only retains the flexibility of software but also the scalability of hardware. In existing primitives, the most expressive Push-In-ExtractOut (PIEO) is prohibitively expensive to implement due to its complexity. While its variant, Push -In -Pick -Out (PIPO), offers some improvements, it suffers from insufficient scalability. In this paper, we propose the ClassifyIn -Push -Out (CIPO) primitive. The core idea of CIPO is to track the rank and predicate of recent packets through a sliding window, filter and classify packets using a prediction -based two-dimensional classification algorithm and a finite number of First -In -First -Out (FIFO) queues. Through theoretical analysis and evaluation with a range of real workloads, CIPO proves that it has a scheduling performance similar to the most expressive scheduling primitive. Importantly, CIPO requires fewer hardware resources while still providing sufficient expressiveness. Primitive on FPGA show that the CIPO-based scheduler achieves an average of 1 . 24x higher throughput than the PIEO-based scheduler but uses only an average of 26.2% of look -up tables (LUTs) and 12.2% of the block RAM of the latter.
programmablepacket schedulers have emerged in the context of Software -Defined Networking (SDN) and diverse service requirements in today's networks. With a programmablepacket scheduler, network operators can ap...
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programmablepacket schedulers have emerged in the context of Software -Defined Networking (SDN) and diverse service requirements in today's networks. With a programmablepacket scheduler, network operators can apply different scheduling algorithms on the switches. To support a large variety of packetscheduling algorithms, the use of a packet scheduler like PIFO (Push -In First -Out) has been adopted, which serves packets based on their associated priority ranks. Recently, for the concern of priority rank scalability and implementation complexity, a new class of packet schedulers that closely approximate PIFO have been proposed. However, the approximate PIFO schemes may lead to a sub -optimal packetscheduling order and introduce packet inversions. In this paper, we evaluate the inversion impact on Start -Time Fair Queueing (STFQ), an efficient approximation of Weighted Fair Queueing to allocate bandwidth fairly and achieve low maximum delay, when it is used in the approximate PIFO schemes. Our analysis validates the deterioration on the performance goals of STFQ attributed to packet inversions and provides a theoretical bound for the discrepancy caused by these inversions in the fair and delay guarantees offered by STFQ. Based on our simulation results, we demonstrate that the packet inversions in approximate PIFO schemes impair the fairness of bandwidth allocation and the worst -case throughput difference in our simulation exhibits a bias of up to 34% of the total available bandwidth. We further show that the packet inversions result in a 3 -fold increase in the maximum end -to -end packet delay in approximate PIFO schemes such as SP-PIFO and AFQ.
With increasing link speeds and slowdown in the scaling of CPU speeds, packetscheduling in software is resulting in lower precision and higher CPU utilization. By offloading packetscheduling to the hardware such as ...
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ISBN:
(纸本)9781450359566
With increasing link speeds and slowdown in the scaling of CPU speeds, packetscheduling in software is resulting in lower precision and higher CPU utilization. By offloading packetscheduling to the hardware such as a NIC, one can potentially overcome these drawbacks. However, to retain the flexibility of software packet schedulers, packet scheduler in hardware must be programmable, while also being fast and scalable. State-of-the-art packet schedulers in hardware either compromise on scalability (Push-In-First-Out (PIFO)) or the ability to express a wide range of packetscheduling algorithms (First-In-First-Out (FIFO)). Further, even a general scheduling primitive like PIFO is not expressive enough to express certain key classes of packetscheduling algorithms. Hence in this paper, we propose a generalization of the PIFO primitive, called Push-In-Extract-Out (PIEO), which like PIFO, maintains an ordered list of elements, but unlike PIFO which only allows dequeue from the head of the list, PIEO allows dequeue from arbitrary positions in the list by supporting a programmable predicate-based filtering at dequeue. Next, we present a fast and scalable hardware design of PIEO scheduler and prototype it on a FPGA. Overall, PIEO scheduler is both more expressive and over 30x more scalable than PIFO.
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