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Lightweight Named Object: An ICN-Based Abstraction for IoT Device programming and Management

IEEE INTERNET OF THINGS JOURNAL 2019年第3期6卷 5029-5039页

作者： Bracciale, Lorenzo Loreti, Pierpaolo Detti, Andrea Paolillo, Riccardo Melazzi, Nicola Blefari Univ Roma Tor Vergata Dept Elect Engn I-00133 Rome Italy Consorzio Nazl Interuniv Telecomunicaz UDR Roma Tor Vergata I-00133 Rome Italy

The expected dramatic growth of connected things raises the issue of how to efficiently organize them, in order to monitor and manage functions and interactions. Information centric networking (ICN) is a communication paradigm that provides content-oriented functionality in the network and at the network level, including content routing, caching, multicast, mobility, data-centric security, and a flexible namespace. Thus, it is a viable solution for supporting Internet of Things (IoT) services without requiring any centralized entity. In this paper, we introduce the lightweight named object solution: a convenient way to represent physical IoT objects in a derived name space, exploiting ICN. We show that this abstraction can: 1) increase the programming simplicity;2) offer extended functionality, such as augmentation and upgrading, to cope with the "software erosion," and 3) implement a common interaction logic involving mutual function invocation. We present some proof-of-concept implementations of the proposed abstraction dealing with challenging IoT test cases;we also carry out a performance evaluation in a simulated network scenario.

关键词： Augmentation data-centric security distributed objects information centric networking (ICN) Internet of Things (IoT) named data networking (NDN) naming programming language

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SPECIFICATION AND VERIFICATION OF DIGITAL-SYSTEMS USING HIGHER-ORDER PREDICATE LOGIC

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IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES 1986年第5期133卷 242-254页

作者： HANNA, FK DAECHE, N Electronic Engineering Laboratories University of Kent Canterbury UK

The paper describes how higher-order predicate logic may be used to specify both the structure and the behaviour of a digital system, and to reason about their interrelationship. The overall approach is named VERITAS; the paper concentrates particularly on describing its methodological aspects. The behaviour of a system is specified by a predicate on the analogue waveforms at the ports of the system. In general, behavioural specifications are partial. The internal structure of a system is defined by a set of projection functions that yield its component parts, together with a set of equations describing their interconnections. Reasoning about the behavioural properties of digital systems is carried out within the framework of an axiomatic theory that describes relevant properties of arithmetic, time, waveforms and structures. The logic is embedded within a programming language, MV, whose data types include signature, term and derivation. This allows inferencing to be carried out computationally, which in turn guarantees its correctness.

关键词： arithmetic digital systems specification computer testing higher-order predicate logic programming language projection functions axiomatic theory analogue waveforms Performance evaluation and testing structures waveforms MV VERITAS time verification

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A high-speed-execution method for a program written in factory-automation-cell control language

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ELECTRICAL ENGINEERING IN JAPAN 2003年第2期144卷 34-42页

作者： Koyama, M Miyake, N Fujii, K Komoda, N Osaka Univ Grad Sch Informat Sci & Technol Suita Osaka 565 Japan

A new programming method called Cell Control language (CCL) for factory-automation systems has been developed. In CCL programming, an action sequence of each functional unit in each operation mode is first described as a net module. This net module is a subclass of Petri nets, and this subclass is equivalent to a state-transition diagram (a conventional design method). Several net modules are merged and translated into an internal code program, which is executed in a cell controller. To improve the ability of the controller to respond to state changes, we developed two new methods based on CCL. One is that for efficiently describing a CCL program, which needs a quick response to state changes, and the other is that for executing the program in a short cycle. The execution method was applied to an actual cell controller, which confirmed that it can improve the ability to respond to state changes without reducing the total control performance. (C) 2003 Wiley Periodicals, Inc.

关键词： Petri net factory automation (FA) sequence control programming language interruption process

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A bottom-up approach to verifiable embedded system information flow security

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IET INFORMATION SECURITY 2014年第1期8卷 12-17页

作者： Mu, Dejun Hu, Wei Mao, Baolei Ma, Bo Northwestern Polytech Univ Sch Automat Xian 710072 Peoples R China

With the wide deployment of embedded systems and constant increase in their inter-connections, embedded systems tend to be confronted with attacks through security holes that are hard to predict using typical security measures such as access control or data encryption. To eliminate these security holes, embedded security should be accounted for during the design phase from all abstraction levels with effective measures taken to prevent unintended interference between different system components caused by harmful flows of information. This study proposes a bottom-up approach to designing verifiably information flow secure embedded systems. The proposed method enables tight information flow controls by monitoring all flows of information from the level of Boolean gates. It lays a solid foundation to information flow security in the underlying hardware and exposes the ability to prove security properties to all abstraction levels in the entire system stack. With substantial amounts of modifications made to the instruction set architecture, operating system, programming language and input/output architecture, the target system can be designed to be verifiably information flow secure.

关键词： embedded systems formal verification instruction sets operating systems (computers) security of data bottom up approach verifiable embedded system information flow security security holes access control data encryption information flow controls instruction set architecture operating system programming language input-output architecture

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A NEW programming PARADIGM FOR ENGINEERING DESIGN SOFTWARE

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ENGINEERING WITH COMPUTERS 1994年第2期10卷 95-111页

作者： SALUSTRI, FA VENTER, RD 1. Department of Mechanical Engineering University of Toronto 5 King's College Road M5S 1A4 Toronto Ontario Canada

Currently available programming and database systems are insufficient for engineering applications. The authors contend that a logical progression from a formal conceptual model of the engineering domain to a computational model will lead to new programming paradigms capable of directly supporting engineering applications in a rigorous, concise manner. A formal domain model devised by the authors, the Hybrid Model (HM) of design information, is briefly introduced. It is an extension of axiomatic set theory and is discussed in detail elsewhere. HM forms the basis of Designer, a prototype-based object-oriented programming language supporting a signature-based canonical message-passing mechanism and multiple inheritance. Designer is implemented using the Scheme programming language. Because Designer satisfies a formal conceptual model, and because it is based on a formally specified language, its robustness and logical validity are superior to those of other languages not founded on formal principles. Designer combines concepts of functional and object-oriented programming to provide the formal rigor and flexibility to capture the complex and strongly interrelated information that designers use. Examples demonstrate how Designer represents design information. The results of the authors' research indicate that Designer can capture design information (including aspects of functional requirements and design intent) effectively and efficiently.

关键词： ENGINEERING DESIGN FORMAL FUNCTIONAL programming OBJECT ORIENTATION programming language

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FPGA-based implementation of bistable function blocks defined in the IEC 61131

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MICROPROCESSORS AND MICROSYSTEMS 2019年 65卷 37-46页

作者： Chmiel, M. Silesian Tech Univ Inst Elect Akad Str 16 PL-44100 Gliwice Poland

This article discusses the possibilities of using FPGAs in order to construct fast PLCs that execute serial-cyclic program control loop. The PLCs bistable function blocks of the IEC 61131-3 standard with particular emphasis on the possible FPGA implementations are presented. The FPGA hardware support is implemented in such a way that it does not interfere with the normal, serial-cyclic program execution. It enables a significant reduction in the timing of the result execution after loading new input data in the memory cells. Moreover, such an implementation of bistable function blocks allows for seamless use in any programming language. Both the IL text language and the graphical languages (LD and FBD) can freely use the advantages of such a solution. (C) 2018 Elsevier B.V. All rights reserved.

关键词： Programmable logic controllers (PLC) IEC 61131 programming language Field programmable gate arrays (FPGA) Bistable function blocks

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Stepwise-refinement for performance: a methodology for many-core programming

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CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2015年第17期27卷 4515-4554页

作者： Hijma, P. van Nieuwpoort, R. V. Jacobs, C. J. H. Bal, H. E. Vrije Univ Amsterdam Dept Comp Sci Amsterdam Netherlands Netherlands eSci Ctr Amsterdam Netherlands

Many-core hardware is targeted specifically at obtaining high performance, but reaching high performance is often challenging because hardware-specific details have to be taken into account. Although there are many programming systems that try to alleviate many-core programming, some providing a high-level language, others providing a low-level language for control, none of these systems have a clear and systematic methodology as a foundation. In this article, we propose stepwise-refinement for performance: a novel, clear, and structured methodology for obtaining high performance on many-cores. We present a system that supports this methodology, offers multiple levels of abstraction to provide programmers a trade-off between high-level and low-level programming, and provides programmers detailed performance feedback. We evaluate our methodology with several widely varying compute kernels on two different many-core architectures: a Graphical Processing Unit (GPU) and the Xeon Phi. We show that our methodology gives insight in the performance, and that in almost all cases, we gain a substantial performance improvement using our methodology. Copyright (c) 2015 John Wiley & Sons, Ltd.

关键词： methodology stepwise-refinement many-core programming language hardware description abstraction levels

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Adaptative parallel simulators for bioinspired computing models

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FUTURE GENERATION COMPUTER SYSTEMS-THE INTERNATIONAL JOURNAL OF ESCIENCE 2020年 107卷 469-484页

作者： Martinez-del-Amor, Miguel A. Perez-Hurtado, Ignacio Orellana-Martin, David Perez-Jimenez, Mario J. Univ Seville Dept Comp Sci & Artificial Intelligence Res Grp Nat Comp Seville Spain

In the Membrane Computing area, P systems are unconventional devices of computation inspired by the structure and processes taking place in living cells. Main successful P system applications lie in computability and computational complexity theories, as well as in biological modelling. Given that models become too complex to deal with, simulators for P systems are essential tools and their efficiency is critical. In order to handle the diverse situations that may arise during the computation, these simulators have to take into account that worst-case scenarios can happen, even though they rarely occur. As a result, there is a significant loss of performance. In this paper, the concept of adaptative simulation for P systems is introduced to palliate this problem. This is achieved by passing high-level information provided directly by P system model designers to the simulator, helping it to better adapt to the target model. For this purpose, an existing simulator for an ecosystem modelling framework, named Population Dynamics P systems, is extended to include the information of modules, that are usually employed to define ecosystem models. Moreover, the standard description language for P systems, P-Lingua, has been re-engineered in its version 5. It now includes a new syntactical item, called feature, to express this kind of high-level semantic information. Experiments show that this simple adaptative simulator supporting modules as features doubles the performance when running on GPUs and on multicore processors. (C) 2020 Elsevier B.V. All rights reserved.

关键词： Bioinspired computing Membrane computing P system programming language Parallel computing GPU computing

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LEAD: A language for dynamically adaptable applications

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 1998年第6期E81A卷 992-1000页

作者： Amano, N Watanabe, T Graduate School of Information Science Japan Advanced Institute of Science and Technology Ishikava-ken 923-1292 Japan

As open-ended distributed systems and mobile computing systems have spread widely, the need for software which can adapt itself to the dynamic change of runtime environments increases. We call the ability of the software dynamic adaptability. We designed and implemented a language LEAD that provides an architecture for dynamic adaptability. The basic idea is to introduce the mechanism which changes procedure invocation dynamically according to the stales of runtime environments. Using LEAD, we can easily realize 1) the highly extensible dynamically adaptable applications, and 2) the introduction of the dynamic adaptability into existing applications.

关键词： programming language software adaptation meta-level architecture and reflection

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PARSING languageS BY PATTERN-MATCHING

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IEEE TRANSACTIONS ON SOFTWARE ENGINEERING 1988年第4期14卷 498-511页

作者： RUS, T Department of Computer Science University of Iowa Iowa City IA 52242

The language of universal algebras is used as an alternative approach for programming language specification. BNF rules are employed for specifying the signature of the language algebra instead of the context free syntax. The algorithm for program parsing is inductively defined by the following universal algebraic construction: Any function defined on the generators of a free algebra taking values in the carrier of another similar algebra can be uniquely extended to a homomorphism between the two algebras. Any conventional programming language can be specified by a finite set of BNF rules and its algebra of symbols is generated by a finite set of generator classes. Thus any function defined on the finite set of generators offers an algebraic mechanism for a universal algorithm for source language program parsing. The right-hand side of the BNF rules are the patterns searched by the algorithm in the source text of the program. The essential feature of this algorithm is that it can be used as a driver for code generation and optimization in a translator. This driver recognizes source language constructs in the source text. The code generator evaluates them into the target language regenerating the source language program inductively as a target language program. Therefore this parser is also called a program evaluator. [ABSTRACT FROM AUTHOR]

关键词： algorithm BNF-rule compiler complexity Index Terms-Algebraic model language pattern matching program evaluation program parsing programming language specification mechanism

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