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Analysing Farm-specific Payments for Norway using the Agrispace model

JOURNAL OF AGRICULTURAL ECONOMICS 2018年第3期69卷 777-793页

作者： Mittenzwei, Klaus Britz, Wolfgang Norwegian Inst Bioecon Res NIBIO Oslo Norway Univ Bonn Inst Food & Resource Econ Bonn Germany

Norway maintains a complex system of activity or type specific coupled payments which account for a large share of farm income. Most of the payment rates are negatively related to farm size and are higher in remote areas compared to central regions. We present and use a newly developed recursive-dynamic multi-commodity model (Agrispace) with CES production functions depicting regional farm clusters derived from the full farm population. Using this model, we simulate impacts of current and alternative subsidy policies on production, prices, input use, income and farm structural change. Mapping cluster results to each farm along with behavioural rules allows estimation of individual profits and farm exits. Our results indicate that, in the short run, the current policy regime seems to support the policy objective of maintaining a variety of farms in all parts of Norway. In the long run, farm structural change is less affected by a policy reform that leaves total support levels unchanged.

关键词： Norway policy reform programming model structural change

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Heterogeneous distributed computing based on high-level abstractions

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CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2018年第17期30卷 e4664.1-e4664.13页

作者： Vinas, M. Fraguela, B. B. Andrade, D. Doallo, R. Univ A Coruna Grupo Arquitectura Comp La Coruna Spain

The rise of heterogeneous systems has given place to great challenges for users as they involve new concepts, restrictions, and frameworks. Their exploitation is further complicated in the context of distributed memory systems, which require the usage of additional different programming paradigms and tools. In this paper, we propose a novel approach to program heterogeneous clusters that is based on high-level abstractions such as tiles and hierarchical decomposition combined with the powerful APIs that data types and embedded languages can provide in languages such as C++. Rather than building our proposal from scratch, we have implemented it as a natural integration of the existing Hierarchically Tiled Arrays (HTA) and Heterogeneous programming Library (HPL) projects, ie, the first one being focused on distributed computing and the second one on heterogeneous processing. The result, called Heterogeneous Hierarchically Tiled Arrays (H(2)TA), is very intuitive and easy to use thanks to the global view of the data and the single-threaded view of the execution that it provides at cluster level together with the transparency it provides with respect to the management of the heterogeneous devices. An evaluation comparing our proposal with MPI-based implementations shows its large programmability advantages and the reasonable overhead incurred.

关键词： data parallelism distributed computing heterogeneous computing OpenCL programming model runtime system

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Towards A Portable Hierarchical View of Distributed Shared Memory Systems: Challenges and Solutions 11

Towards A Portable Hierarchical View of Distributed Shared M...

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11th International Workshop on programming models and Applications for Multicores and Manycores (PMAM)

作者： Ghane, Millad Chandrasekaran, Sunita Cheung, Margaret S. Univ Houston Dept Comp Sci Houston TX 77004 USA Univ Delaware Dept Comp & Informat Sci Newark DE 19716 USA Univ Houston Phys Dept Houston TX 77004 USA Rice Univ Ctr Theoret Biol Phys Houston TX 77251 USA

ISBN: (纸本)9781450375221

An ever-growing diversity in the architecture of modern supercomputers has led to challenges in developing scientific software. Utilizing heterogeneous and disruptive architectures (e.g., off-chip and, in the near future, on-chip accelerators) has increased the software complexity and worsened its maintainability. To that end, we need a productive software ecosystem that improves the usability and portability of applications for such systems while allowing every parallelism opportunity to be exploited. In this paper, we outline several challenges that we encountered in the implementation of Gecko, a hierarchical model for distributed shared memory architectures, using a directive-based programming model, and discuss our solutions. Such challenges include: 1) inferred kernel execution with respect to the data placement, 2) workload distribution, 3) hierarchy maintenance, and 4) memory management. We performed the experimental evaluation of our implementation by using the Stream and Rodinia benchmarks. These benchmarks represent several major scientific software applications commonly used by the domain scientists. Our results reveal how the Stream benchmark reaches a sustainable bandwidth of 80 GB/s and 1.8 TB/s for single Intel Xeon Processor and four NVIDIA V100 GPUs, respectively. Additionally, the srad_v2 in the Rodinia benchmark reaches the 88% speedup efficiency while using four GPUs.

关键词： Hierarchy Heterogeneous Portable Shared Memory programming model Abstraction

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Wide-area real-time distributed computing in a tightly managed optical grid - An optiputer vision

Wide-area real-time distributed computing in a tightly manag...

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18th International Conference on Advanced Information Networking and Applications

作者： Kim, KH Univ Calif Irvine DREAM Lab Dept EECS Irvine CA 92697 USA

ISBN: (纸本)0769520510

Wide area network (WAN) -based distributed computing (DC) has become an active field of research, especially under the label of grid computing. On the other hand, research on WAN-based real-time (RT) DC has remained in an embryonic stage. The situation is changing, however. Continuous increase in the availability of optical channels, called lambdas, along with steady decrease of their costs, have given rise to efforts to establish optical network infrastructure in which the possibility of dynamically allocating entire end-to-end light-paths to different message streams created by a moderate number of important applications is real. With such infrastructure there is no major obstacle in facilitating RT DC. The notion of RT distributed virtual computer (DVC), which can also be viewed as an RT sub-grid, is introduced. Then the challenging issues in adapting some promising technologies established for RT DC in LAN environments to enable realization of RT DVCs in WAN environments are discussed. programming model and resource management are the focus of the discussion.

关键词： real time grid optical network wide area WAN latency guaranteed bandwidth resource management programming model global time object TMO

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Efficient Transaction Nesting in Hardware Transactional Memory

Efficient Transaction Nesting in Hardware Transactional Memo...

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23rd International Conference on Architecture of Computing Systems (ARCS 2010)

作者： Liu, Yi Su, Yangming Zhang, Cui Wu, Mingyu Zhang, Xin Li, He Qian, Depei Beihang Univ Sinogerman Joint Software Inst Beijing 100191 Peoples R China Xi An Jiao Tong Univ Dept Comp Xian 710049 Peoples R China

ISBN: (纸本)9783642119491

Efficient transaction nesting is one of the ongoing challenges for hardware transactional memory. To increase efficiency of closed nesting, this paper proposes a conditional partial rollback (CPR) scheme which supports conditional partial rollback without increasing hardware complexities significantly. In stead of rolling back to the outermost transaction as in commonly-used flattening model, the CPR scheme just rolls back to the conflicted transaction itself or one of its outer-level transactions if given conditions are satisfied. By recording access status of each nested transaction, the scheme uses one global data set for all of the nested transactions rather than independent data set for each nested transaction. Hardware transactional memory architecture with Hie support of CPR scheme is also proposed based on multi-core processor and current cache coherence mechanism. Time system is implemented by simulation, and evaluated using seven benchmark applications. Evaluation results show that the CPR scheme achieves better performance and scalability than the flattening model which is commonly-used in hardware transactional memory.

关键词： transactional memory transaction nesting multi-core processor programming model programmability

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Magellan: Generating Multi-Table Datapath from Datapath Oblivious Algorithmic SDN Policies 16

Magellan: Generating Multi-Table Datapath from Datapath Obli...

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ACM Conference on Special Interest Group on Data Communication (SIGCOMM)

作者： Voellmy, Andreas Chen, Shenshen Wang, Xing Yang, Y. Richard Yale Univ New Haven CT 06520 USA Tongji Univ Shanghai Peoples R China

ISBN: (纸本)9781450341936

Despite the emergence of multi-table pipelining as a key feature of next-generation SDN data-path models, there is no existing work that addresses the substantial programming challenge of utilizing multi-tables automatically. In this paper, we present Magellan, the first system that addresses the aforementioned challenge. Introducing two novel, substantial algorithms, map-explore and table-design, Magellan achieves automatic derivation and population of multi-table pipelines from a datapath-oblivious, high-level SDN program written in a general-purpose language. Comparing the flow tables generated by Magellan with those produced from standard SDN controllers including Open-Daylight and Floodlight, we show that Magellan uses between 46-68x fewer rules.

关键词： SDN programming model Multi-table pipeline

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Efficient and Simplified Parallel Graph Processing over CPU and MIC 29

Efficient and Simplified Parallel Graph Processing over CPU ...

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29th IEEE International Parallel and Distributed Processing Symposium (IPDPS)

作者： Chen, Linchuan Huo, Xin Ren, Bin Jain, Surabhi Agrawal, Gagan Ohio State Univ Dept Comp Sci & Engn Columbus OH 43210 USA

ISBN: (纸本)9781479986484

Intel Xeon Phi (MIC architecture) is a relatively new accelerator chip, which combines large-scale shared memory parallelism with wide SIMD lanes. Mapping applications on a node with such an architecture to achieve high parallel efficiency is a major challenge. In this paper, we focus on developing a system for heterogeneous graph processing, which is able to utilize both a many-core Xeon Phi and a multi-core CPU on one node. We propose a simple programming API with an intuitive interface for expressing SIMD parallelism. We develop efficient techniques for supporting our high-level API, focusing on exploiting wide SIMD lanes, massive number of cores, and partitioning of the work across CPU and accelerator, while handling the irregularity of graph applications. The components of our runtime system include a condensed static memory buffer, which supports efficient message insertion and SIMD message reduction while keeping memory requirements low, and specifically for MIC, a pipelining scheme for efficient message generation by avoiding frequent locking operations. Besides, a hybrid graph partitioning module is able to effectively partition the workload between the CPU and the MIC, ensuring balanced workload and low communication overhead. The main observations from our experimental evaluation using five popular applications are: for MIC executions, pipelining scheme is up to 3.36x faster than a naive approach using locking based message generation, and the speedup over OpenMP ranges from 1.17 to 4.15. Heterogeneous CPU-MIC execution achieves a speedup of up to 1.41 over the better of the CPU-only and MIC-only executions.

关键词： CPU Graph Processing Intel MIC programming model

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MEMODYN: Exploiting Weakly Consistent Data Structures for Dynamic Parallel Memoization 18

MEMODYN: Exploiting Weakly Consistent Data Structures for Dy...

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27th IEEE/ACM/IFIP International Conference on Parallel Architectures and Compilation Techniques (PACT)

作者： Prabhu, Prakash Beard, Stephen R. Apostolakis, Sotiris Zaks, Ayal August, David I. Google India Bengaluru Karnataka India Princeton Univ Princeton NJ 08544 USA Intel Corp Haifa Israel

ISBN: (纸本)9781450359863

Several classes of algorithms for combinatorial search and optimization problems employ memoization data structures to speed up their serial convergence. However, accesses to these data structures impose dependences that obstruct program parallelization. Such programs often continue to function correctly even when queries into these data structures return a partial view of their contents. Weakening the consistency of these data structures can unleash new parallelism opportunities, potentially at the cost of additional computation. These opportunities must, therefore, be carefully exploited for overall speedup. This paper presents MEMODYN, a framework for parallelizing loops that access data structures with weakly consistent semantics. MEMODYN provides programming abstractions to express weak semantics, and consists of a parallelizing compiler and a runtime system that automatically and adaptively exploit the semantics for optimized parallel execution. Evaluation of MEMODYN shows that it achieves efficient parallelization, providing significant improvements over competing techniques in terms of both runtime performance and solution quality.

关键词： Implicit parallelism programming model weakly consistent data structures automatic parallelization memoization runtime adaptivity tuning

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memCUDA: Map Device Memory to Host Memory on GPGPU Platform

memCUDA: Map Device Memory to Host Memory on GPGPU Platform

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IFIP International Conference on Network and Parallel Computing

作者： Jin, Hai Li, Bo Zheng, Ran Zhang, Qin Ao, Wenbing Huazhong Univ Sci & Technol Sch Comp Sci & Technol Cluster & Grid Comp Lab Serv Comp Technol & Syst Lab Wuhan 430074 Peoples R China

ISBN: (纸本)9783642156717

The Compute Unified Device Architecture (CUDA) programming environment from NVIDIA is a milestone towards making programming many-core GPUs more flexible to programmers. However, there are still many challenges for programmers when using CUDA. One is how to deal with GPU device memory, and data transfer between host memory and GPU device memory explicitly. In this study, source-to-source compiling and runtime library technologies are used to implement an experimental programming system based on CUDA, called memCUDA, which can automatically map GPU device memory to host memory. With some pragma directive language, programmer can directly use host memory in CUDA kernel functions, during which the tedious and error-prone data transfer and device memory management are shielded from programmer. The performance is also improved with some near-optimal technologies. Experiment results show that memCUDA programs can get similar effect with well-optimized CUDA programs with more compact source code.

关键词： GPU CUDA memory mapping programming model

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Scalable Embedded Systems: Towards the Convergence of High-Performance and Embedded Computing 13

Scalable Embedded Systems: Towards the Convergence of High-P...

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13th International Conference on Embedded and Ubiquitous Computing (EUC 2015)

作者： Giorgi, Roberto Univ Siena Siena Italy

ISBN: (纸本)9781467382991

Embedded System toolchains are highly customized for a specific System-on-Chip (SoC). When the application needs more performance, the designer is typically forced to adopt a new SoC and possibly another toolchain. The rationale for not scaling performance by using, e.g., two SoCs, is that maintining most of the operations on-chip may allow for higher energy efficiency. We are exploring the feasibility and trade-offs of designing and manufacturing a new Single Board Computer (SBC) that could serve flexibly for a number of current and future applications, by allowing scalability through clusters of SBCs while keeping the same programming model for the SBC. This board is based on FPGAs and embedded processors, and its key points are: i) a fast custom interconnect for board-to-board communication and ii) an easily programmable environment which would allow both the off-loading of code into accelerators (either soft-IP blocks or hard-IP blocks) and, at the same time, the distribution of computation across boards. A key challenge to successfully deploying this paradigm is to properly distribute the threads across several boards without the explicit intervention of the programmer. In this paper we describe how to dynamically and efficiently distribute the computational threads in symbiosis with an appropriate memory model to allow the system scalability, so that we can double the performance by simply connecting two boards without i) changing the basic hardware components (e.g., to a different System-On-Chip) and ii) changing the programming model to follow the vendor specific toolchain. Our approach is to reduce data movement across boards. Our initial experiments have confirmed the feasibility of our approach.

关键词： Cyber-Physical Systems Reconfigurable Systems Cluster programming FPGA programming Distributed Shared Memory programming model Performance Evaluation

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