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Towards a High Level Approach for the programming of Heterogeneous Clusters 45

Towards a High Level Approach for the Programming of Heterog...

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45th International Conference on Parallel Processing (ICPP)

作者： Vinas, Moises Fraguela, Basilio B. Andrade, Diego Doallo, Ramon Univ A Coruna Dept Elect & Sistemas La Coruna Spain

ISBN: (纸本)9781509028252

The programming of heterogeneous clusters is inherently complex, as these architectures require programmers to manage both distributed memory and computational units with a very different nature. Fortunately, there has been extensive research on the development of frameworks that raise the level of abstraction of cluster-based applications, thus enabling the use of programming models that are much more convenient that the traditional one based on message-passing. One of such proposals is the Hierarchically Tiled Array (HTA), a data type that represents globally distributed arrays on which it is possible to perform a wide range of data-parallel operations. In this paper we explore for the first time the development of heterogeneous applications for clusters using HTAs. In order to use a high level API also for the heterogenous parts of the application, we developed them using the Heterogeneous programming Library (HPL), which operates on top of OpenCL but providing much better programmability. Our experiments show that this approach is a very attractive alternative, as it obtains large programmability benefits with respect to a traditional implementation based on MPI and OpenCL, while presenting average performance overheads just around 2%.

关键词： distributed computing heterogeneity data parallelism programming model libraries OpenCL

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The TERAFLUX Project: Exploiting the DataFlow Paradigm in Next Generation Teradevices

The TERAFLUX Project: Exploiting the DataFlow Paradigm in Ne...

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16th Euromicro Conference on Digital System Design (DSD)

作者： Solinas, Marco Badia, Rosa M. Bodin, Francois Cohen, Albert Evripidou, Paraskevas Faraboschi, Paolo Fechner, Bernhard Gao, Guang R. Garbade, Arne Girbal, Sylvain Goodman, Daniel Khan, Behran Koliai, Souad Li, Feng Lujan, Mikel Morin, Laurent Mendelson, Avi Navarro, Nacho Pop, Antoniu Trancoso, Pedro Ungerer, Theo Valero, Mateo Weis, Sebastian Watson, Ian Zuckermann, Stephane Giorgi, Roberto Univ Siena Dip Ingn Informaz & Sci Matemat I-53100 Siena Italy Barcelona Supercomp Ctr Barcelona Spain CAPS Enterprise Paris France INRIA Paris France Univ Cyprus CY-1678 Nicosia Cyprus Intelligent Infrastructure Lab Hewlett Packard Barcelona Spain Univ Augsburg Augsburg Germany Univ Delaware Delaware OH USA THALES Paris France Univ Manchester Manchester Lancs England Techn Jerusalem Israel

ISBN: (纸本)9780769550749

Thanks to the improvements in semiconductor technologies, extreme-scale systems such as teradevices (i.e., composed by 1000 billion of transistors) will enable systems with 1000+ general purpose cores per chip, probably by 2020. Three major challenges have been identified: programmability, manageable architecture design, and reliability. TERAFLUX is a Future and Emerging Technology (FET) large-scale project funded by the European Union, which addresses such challenges at once by leveraging the dataflow principles. This paper describes the project and provides an overview of the research carried out by the TERAFLUX consortium.

关键词： TERAFLUX dataflow programming model compilation reliability architecture simulation many-cores exascale computing multi-cores

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Hierarchical Management of Extreme-Scale Task-Based Applications 29th

Hierarchical Management of Extreme-Scale Task-Based Applicat...

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29th International Conference on Parallel and Distributed Computing (Euro-Par)

作者： Lordan, Francesc Puigdemunt, Gabriel Verges, Pere Conejero, Javier Ejarque, Jorge Badia, Rosa M. Barcelona Supercomp Ctr Barcelona Spain Univ Calif Irvine Irvine CA USA

ISBN: (纸本)9783031396977;9783031396984

The scale and heterogeneity of exascale systems increment the complexity of programming applications exploiting them. Task-based approaches with support for nested tasks are a good-fitting model for them because of the flexibility lying in the task concept. Resembling the hierarchical organization of the hardware, this paper proposes establishing a hierarchy in the application workflow for mapping coarse-grain tasks to the broader hardware components and finer-grain tasks to the lowest levels of the resource hierarchy to benefit from lower-latency and higher-bandwidth communications and exploiting locality. Building on a proposed mechanism to encapsulate within the task the management of its finer-grain parallelism, the paper presents a hierarchical peer-to-peer engine orchestrating the execution of workflow hierarchies with fully-decentralized management. The tests conducted on the MareNostrum 4 supercomputer using a prototype implementation prove the validity of the proposal supporting the execution of up to 707,653 tasks using 2,400 cores and achieving speedups of up to 106 times faster than executions of a single workflow and centralized management.

关键词： distributed systems exascale task-based programming model workflow hierarchy runtime system peer-to-peer decentralized management

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StreamDrive: A Dynamic Dataflow Framework For Clustered Embedded Architectures 17

StreamDrive: A Dynamic Dataflow Framework For Clustered Embe...

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14th ACM International Conference on Computing Frontiers

作者： Stoutchinin, Arthur Benini, Luca ST Microelect Grenoble France Univ Bologna Dipartimento Ingn Energia Elettr & Inform Bologna Italy

ISBN: (纸本)9781450344876

In this paper, we present StreamDrive, a dynamic dataflow framework for programming clustered embedded multicore architectures. StreamDrive simplifies development of dynamic dataflow applications starting from sequential reference C code and allows seamless handling of heterogeneous and application-specific processing elements at the application level. We address issues of efficient implementation of the dynamic dataflow runtime system in the context of constrained embedded environments, which have not been sufficiently addressed by previous research. We conducted a detailed performance evaluation of the StreamDrive implementation on our Application Specific MultiProcessor (ASMP) cluster using the Oriented FAST and Rotated BRIEF (ORB) algorithm typical of image processing domain. Our implementation has less than 10% parallelization overhead, near linear speed-up when the number of processors increases from 1 to 8, and achieves the performance of 15 VGA frames per second with a small cluster configuration of 4 processing elements and 64KB of shared memory, and of 30 VGA frames per second with 8 processors and 128KB of shared memory.

关键词： image processing embedded multicore dataflow programming model

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Design and Implementation of Data Flow programming Language DFC2 23

Design and Implementation of Data Flow Programming Language ...

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52nd International Conference on Parallel Processing (ICPP)

作者： Luo, Qiuming Liu, Senhong He, Weikai Du, Zheng Shenzhen Univ Coll Comp Sci & Software Engn Shenzhen Guangdong Peoples R China Tsinghua Univ Dept Comp Sci & Technol Beijing Peoples R China

ISBN: (纸本)9798400708428

This article presents the design and development of a dataflow programming language called DFC2 (DataFlow C, version 2) based on the dataflow programming model. The DFC2 compiler is responsible for converting the DFC2 language into C++ language, which is then compiled into an executable file by the C++ compiler. DFC2 is designed to be user-friendly and easy to use by adhering to the traditional imperative programming language model. It also allows for the reuse of existing C language code to reduce development costs. DFC2 distinguishes between graph functions, which are automatically parallelized, and func functions, which are not, giving users greater control over the level of parallelism. Users can describe dataflow graphs at both the inter-function and intra-function levels. This article also implements an optimization framework for the DFC2 compiler and analyzes the optimization results. It demonstrates that with the introduction of conditional constant propagation and dead code elimination, it is possible to reduce execution time by up to 30% in the best-case scenario and an average of approximately 6%.

关键词： programming model Dataflow execution model Dataflow programming language DFC2 language

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τC: C with Process Network Extensions for Embedded Manycores

τC: C with Process Network Extensions for Embedded Manycore...

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14th Annual International Conference on Computational Science

作者： Goubier, Thierry Courousse, Damien Azaiez, Selma CEA LIST DACLE Lastre F-91191 Gif Sur Yvette France CEA LIST DACLE LIALP Grenoble France

Current and future embedded manycore systems bring complex and heterogeneous architectures with a large number of processing cores, making both parallel programming at this scale and understanding the architecture itself a daunting task. Process Networks and other dataflow based models of Computation (MoC) are a good base to present a universal model of the underlying manycore architectures to the programmer. If a language exposes a simple to grasp MoC in a consistent way across architectures, the programmer can concentrate the efforts on optimizing the expression of parallelism in the application instead of porting code to a given system. In this paper, we present a process network extension to C called tau C and its mapping to both a POSIX target and the P2012/STHORM platform, and show how the language offers an architecture independent solution of this problem.

关键词： manycore programming model process networks compiler toolchain

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Fundamental research challenges in real-time distributed computing

Fundamental research challenges in real-time distributed com...

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10th IEEE International Workshop on Future Trends of Distributed Computing Systems (FTDCS 2004)

作者： Kim, KH Univ Calif Irvine Dept EECS DREAM Lab Irvine CA 92697 USA

ISBN: (纸本)0769521185

The author presents a personal perspective on where research efforts are most urgently needed to advance the fundamental foundation for real-time distributed computing. At the top level the biggest fundamental research challenge is to enable high-level high-precision real-time distributed software design and programming accompanied by cost-effective guaranteeing of acceptable response times. This top-level goal cannot be realized without successful development of some key component technologies such as programming model and API and middleware possessing effective resource management capabilities. The state of the art and the promising research directions established by the community in those component technology areas are reviewed. The main type of network environments in which real-time computing applications have been realized are the LAN environments. Newly emerging network environments such as sensor networks at one end and optical grids at the other end add additional dimensions to the challenges posed to the research community. Those additional dimensions are also briefly reviewed.

关键词： real time distributed computing grid object LAN WAN sensor latency guarantee response times resource management programming model global time high level coordination

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Impact of Middleware Design on the Communication Performance 12th

Impact of Middleware Design on the Communication Performance

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12th International Conference on Green, Pervasive, and Cloud Computing (GPC)

作者： Garcia-Valls, Marisol Garrido, Daniel Diaz, Manuel Univ Carlos III Madrid Leganes Spain Univ Malaga Malaga Spain

ISBN: (纸本)9783319571867;9783319571850

The precise architectural approach of a communication middleware technology is of outmost importance in areas where a certain degree of control over the underlying platform is needed, e.g., for fine-grain management of temporal behavior or concurrency management. The design of the middleware libraries and, especially, the resulting execution environment that these provide affect the control level of the application code over the platform resources. In this paper, we describe and analyze the two main design approaches of communication middleware implementations, that offer two different execution environments to applications: direct execution and virtual machine intermediation. We exemplify this idea with a selected set of technologies that does not intend to be exhaustive, but simply representative of both possible middleware architectural design approaches. The goal is to show the impact of these architectures on the resulting communication performance, that we show as overhead, i.e., the percentage of time taken by both architectures with respect to a fixed remote operation with a fixed processing time.

关键词： Middleware Run time Design Communication Performance programming model Real-time

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Mint: An Accelerator For Mining Temporal Motifs 55

Mint: An Accelerator For Mining Temporal Motifs

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55th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Talati, Nishil Ye, Haojie Vedula, Sanketh Chen, Kuan-Yu Chen, Yuhan Liu, Daniel Yuan, Yichao Blaauw, David Bronstein, Alex Mudge, Trevor Dreslinski, Ronald Univ Michigan Comp Sci & Engn Ann Arbor MI 48109 USA Technion Israel Inst Technol Comp Sci Dept Haifa Israel Univ Michigan Elect & Comp Engn Ann Arbor MI USA

ISBN: (数字)9781665462723

ISBN: (纸本)9781665462723

A variety of complex systems, including social and communication networks, financial markets, biology, and neuroscience are modeled using temporal graphs that contain a set of nodes and directed timestamped edges. Temporal motifs in temporal graphs are generalized from subgraph patterns in static graphs in that they also account for edge ordering and time duration, in addition to the graph structure. Mining temporal motifs is a fundamental problem used in several application domains. However, existing software frameworks offer suboptimal performance due to high algorithmic complexity and irregular memory accesses of temporal motif mining. This paper presents Mint-a novel accelerator architecture and a programming model for mining temporal motifs efficiently. We first divide this workload into three fundamental tasks: search, book-keeping, and backtracking. Based on this, we propose a task-centric programming model that enables decoupled, asynchronous execution. This model unlocks massive opportunities for parallelism, and allows storing task context information on-chip. To best utilize the proposed programming model, we design a domain-specific hardware accelerator using its data path and memory subsystem design to cater to the unique workload characteristics of temporal motif mining. To further improve performance, we propose a novel optimization called search index memoization that significantly reduces memory traffic. We comprehensively compare the performance of Mint with state-of-the-art temporal motif mining software frameworks (both approximate and exact) running on both CPU and GPU, and show 9 x-2576 x benefit in performance.

关键词： hardware accelerator programming model temporal motif mining

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The Wild West: Conquest of complex Hardware-dependent Software design

The Wild West: Conquest of complex Hardware-dependent Softwa...

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46th ACM/IEEE Design Automation Conference (DAC 2009)

作者： Yagi, Hiroyuki Engblom, Jakob Serughetti, Marc Andrews, Jason Rosenstiel, Wolfgang Vissers, Kees Sony Corp Atsugi Kanagawa Japan Virtutech AB Stockholm Sweden CoWare Inc San Jose CA USA Cadence Design Syst Inc Ham Lake MN USA Univ Tubingen Tubingen Germany Xilinx Inc San Jose CA USA

ISBN: (纸本)9781605584973

Embedded SW design can be compared to the lawless wild west. With no clear methodology and no standard multi core platform modeling environment every company has to improvise its own solution. The problems facing embedded software users are becoming more complex since: • Hardware platforms become very complicated with many heterogeneous processors, complicated memory structure and interconnect • Multiple platform configurations and platform migrations drive an explosion of the number of version that need to be developed/ maintained/ported • Processors are becoming very complicated and hard to program • Semiconductor vendors can not justify the investment required to provide a complete Hardware Abstraction Layer (HAL), RTOS, etc. • It is hard to put together an embedded software development environment (platform model + HAL+ development tools) • The speed required for efficient software development is very high This panel composed of experts in the problem and solution domains will discuss the current problems and potential solutions. Copyright 2009 ACM.

关键词： Hardware-dependent Software Multiprocessors Multi-core Many-core MPSoC programming model ESL Virtual Prototyping Virtual platform Virtualization heterogeneous/homogenous multi-core symmetric/asymmetric multi-core

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