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EXA2PRO: A Framework for High Development Productivity on Heterogeneous Computing Systems

IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2022年第4期33卷 792-804页

作者： Papadopoulos, Lazaros Soudris, Dimitrios Kessler, Christoph Ernstsson, August Ahlqvist, Johan Vasilas, Nikos Papadopoulos, Athanasios, I Seferlis, Panos Prouveur, Charles Haefele, Matthieu Thibault, Samuel Salamanis, Athanasios Ioakimidis, Theodoros Kehagias, Dionysios Natl Tech Univ Athens Dept Elect & Comp Engn Athens Greece Linkoping Univ Dept Comp & Informat Sci Linkoping Sweden Ctr Res & Technol Hellas Chem Proc & Energy Resources Inst Thessaloniki Greece CEA CNRS Maison Simulat F-75794 Paris France Univ Pau & Pays Adour Lab Math & Its Applicat F-64000 Pau France Bordeaux Univ Bordeaux France Ctr Res & Technol Hellas Informat Technol Inst Thessaloniki Greece

programming upcoming exascale computing systems is expected to be a major challenge. New programming models are required to improve programmability, by hiding the complexity of these systems from application developers. The EXA2PRO programming framework aims at improving developers' productivity for applications that target heterogeneous computing systems. It is based on advanced programming models and abstractions that encapsulate low-level platform-specific optimizations and it is supported by a runtime that handles application deployment on heterogeneous nodes. It supports a wide variety of platforms and accelerators (CPU, GPU, FPGA-based Data-Flow Engines), allowing developers to efficiently exploit heterogeneous computing systems, thus enabling more HPC applications to reach exascale computing. The EXA2PRO framework was evaluated using four HPC applications from different domains. By applying the EXA2PRO framework, the applications were automatically deployed and evaluated on a variety of computing architectures, enabling developers to obtain performance results on accelerators, test scalability on MPI clusters and productively investigate the degree by which each application can efficiently use different types of hardware resources.

关键词： programming Skeleton Computational modeling Runtime Exascale computing Task analysis Productivity programming models skeleton programming task-based runtime systems programming productivity heterogeneous systems exascale computing

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MAGMA templates for scalable linear algebra on emerging architectures

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INTERNATIONAL JOURNAL OF HIGH PERFORMANCE COMPUTING APPLICATIONS 2020年第6期34卷 645-658页

作者： Al Farhan, Mohammed Abdelfattah, Ahmad Tomov, Stanimire Gates, Mark Sukkari, Dalal Haidar, Azzam Rosenberg, Robert Dongarra, Jack Univ Tennessee Innovat Comp Lab ICL Knoxville TN 37996 USA Univ Tennessee Innovat Comp Lab Knoxville TN 37996 USA Univ Tennessee Elect Engn & Comp Sci Dept Comp Sci Knoxville TN 37996 USA Nvidia Corp Santa Clara CA USA Naval Res Lab Ctr Computat Sci CCS Washington DC 20375 USA Oak Ridge Natl Lab Comp Sci & Math Div Oak Ridge TN USA Univ Manchester Manchester Lancs England

With the acquisition and widespread use of more resources that rely on accelerator/wide vector-based computing, there has been a strong demand for science and engineering applications to take advantage of these latest assets. This, however, has been extremely challenging due to the diversity of systems to support their extreme concurrency, complex memory hierarchies, costly data movement, and heterogeneous node architectures. To address these challenges, we design a programming model and describe its ease of use in the development of a newMAGMA Templateslibrary that delivers high-performance scalable linear algebra portable on current and emerging architectures. MAGMA Templates derives its performance and portability by (1) building on existing state-of-the-art linear algebra libraries, like MAGMA, SLATE, Trilinos, and vendor-optimized math libraries, and (2) providing access (seamlessly to the users) to the latest algorithms and architecture-specific optimizations through a single, easy-to-use C++-based API.

关键词： Accelerator-driven computing HPC linear algebra performance portability polymorphism programming models

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HSim: A MapReduce simulator in enabling Cloud Computing

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FUTURE GENERATION COMPUTER SYSTEMS-THE INTERNATIONAL JOURNAL OF ESCIENCE 2013年第1期29卷 300-308页

作者： Liu, Yang Li, Maozhen Alham, Nasullah Khalid Hammoud, Suhel Brunel Univ Sch Engn & Design Uxbridge UB8 3PH Middx England Tongji Univ Key Lab Embedded Syst & Serv Comp Minist Educ Shanghai 200092 Peoples R China

MapReduce is an enabling technology in support of Cloud Computing. Hadoop which is a MapReduce implementation has been widely used in developing MapReduce applications. This paper presents HSim, a MapReduce simulator which builds on top of Hadoop. HSim models a large number of parameters that can affect the behaviors of MapReduce nodes, and thus it can be used to tune the performance of a MapReduce cluster. HSim is validated with both benchmark results and user customized MapReduce applications. (C) 2011 Elsevier B.V. All rights reserved.

关键词： MapReduce Hadoop framework Cloud Computing Simulator programming models

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Kokkos 3: programming Model Extensions for the Exascale Era

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2022年第4期33卷 805-817页

作者： Trott, Christian R. Lebrun-Grandie, Damien Arndt, Daniel Ciesko, Jan Dang, Vinh Ellingwood, Nathan Gayatri, Rahulkumar Harvey, Evan Hollman, Daisy S. Ibanez, Dan Liber, Nevin Madsen, Jonathan Miles, Jeff Poliakoff, David Powell, Amy Rajamanickam, Sivasankaran Simberg, Mikael Sunderland, Dan Turcksin, Bruno Wilke, Jeremiah Sandia Natl Labs POB 5800 Albuquerque NM 87185 USA Oak Ridge Natl Lab POB 2009 Oak Ridge TN 37830 USA Lawrence Berkeley Natl Lab NERSC Berkeley CA 94720 USA Lawrence Berkeley Natl Lab Natl Energy Res Sci Comp Ctr Berkeley CA 94720 USA Argonne Natl Lab Lemont IL 60439 USA Swiss Natl Supercomp Ctr CH-6900 Lugano Switzerland

As the push towards exascale hardware has increased the diversity of system architectures, performance portability has become a critical aspect for scientific software. We describe the Kokkos Performance Portable programming Model that allows developers to write single source applications for diverse high-performance computing architectures. Kokkos provides key abstractions for both the compute and memory hierarchy of modern hardware. We describe the novel abstractions that have been added to Kokkos version 3 such as hierarchical parallelism, containers, task graphs, and arbitrary-sized atomic operations to prepare for exascale era architectures. We demonstrate the performance of these new features with reproducible benchmarks on CPUs and GPUs.

关键词： programming Hardware Kernel Graphics processing units Layout Laboratories Benchmark testing Performance portability programming models high-performance computing heterogeneous computing exascale

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AIRA: A Framework for Flexible Compute Kernel Execution in Heterogeneous Platforms

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2018年第2期29卷 269-282页

作者： Lyerly, Robert Murray, Alastair Barbalace, Antonio Ravindran, Binoy Virginia Tech Dept Elect & Comp Engn Blacksburg VA 24061 USA

Heterogeneous-ISA computing platforms have become ubiquitous, and will be used for diverse workloads which render static mappings of computation to processors inadequate. Dynamic mappings which adjust an application's usage in consideration of platform workload can reduce application latency and increase throughput for heterogeneous platforms. We introduce AIRA, a compiler and runtime for flexible execution of applications in CPU-GPU platforms. Using AIRA, we demonstrate up to a 3.78x speedup in benchmarks from Rodinia and Parboil, run with various workloads on a server-class platform. Additionally, AIRA is able to extract up to an 87 percent increase in platform throughput over a static mapping.

关键词： Heterogeneous architectures compilers runtimes programming models

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A Proposal to Extend the OpenMP Tasking Model with Dependent Tasks

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INTERNATIONAL JOURNAL OF PARALLEL programming 2009年第3期37卷 292-305页

作者： Duran, Alejandro Ferrer, Roger Ayguade, Eduard Badia, Rosa M. Labarta, Jesus Barcelona Supercomp Ctr Dept Comp Sci Barcelona Spain Univ Politecn Cataluna Dept Arquitectura Comp Barcelona Spain CSIC Barcelona Spain

Tasking in OpenMP 3.0 has been conceived to handle the dynamic generation of unstructured parallelism. New directives have been added allowing the user to identify units of independent work (tasks) and to define points to wait for the completion of tasks (task barriers). In this document we propose extensions to allow the runtime detection of dependencies between generated tasks, broading the range of applications that can benefit from tasking or improving the performance when load balancing or locality are critical issues for performance. The proposed extensions are evaluated on a SGI Altix multiprocessor architecture using a couple of small applications and a prototype runtime system implementation.

关键词： OpenMP Task parallelism programming models Tasks synchronization

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STEEL-RT: combining single task-single executor model and expanded scheduling to ease heterogeneity exploitation

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JOURNAL OF SUPERCOMPUTING 2020年第6期76卷 4682-4700页

作者： Rey, Anton Igual, Francisco D. Prieto-Matias, Manuel Univ Complutense Madrid Dept Arquitectura Comp & Automat Madrid 28040 Spain

The ever-increasing complexity in terms of heterogeneity and available parallelism of modern architectures, together with the growing software ecosystem in terms of application libraries and runtime systems are posing a new challenge in terms of programmability on top of the already difficult task of extracting high parallel performance. With the goal of simplifying the programmability at the extreme, we first present the single task-single executor (STSE) model, in which the execution entry point consists solely on a single task assigned to an abstract execution context or executor, representing the whole system platform. As a second contribution, we introduce the expanded scheduling operations that endow executors with additional runtime task scheduling capabilities, and explain how executors can be composed to express and exploit different architectural features at run time under the framework of a single/multiple-task/executor taxonomy. As a result, we introduce STEEL, a novel programming model built on these concepts and STEEL-RT, a coupled high-performance runtime implementation for it. We illustrate the potential of STEEL by means of runtime experiments on a modern heterogeneous architecture, showing that complex and efficient heterogeneous executions are accessible from a STSE approach.

关键词： Heterogeneous computing programming models Data partitioning Thread parallelism Task parallelism

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IRIS: A Performance-Portable Framework for Cross-Platform Heterogeneous Computing

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2024年第10期35卷 1796-1809页

作者： Kim, Jungwon Lee, Seyong Johnston, Beau Vetter, Jeffrey S. NVIDIA Santa Clara CA 95051 USA Oak Ridge Natl Lab Comp Sci & Math Div Oak Ridge TN 37831 USA

From edge to exascale, computer architectures are becoming more heterogeneous and complex. The systems typically have fat nodes, with multicore CPUs and multiple hardware accelerators such as GPUs, FPGAs, and DSPs. This complexity is causing a crisis in programming systems and performance portability. Several programming systems are working to address these challenges, but the increasing architectural diversity is forcing software stacks and applications to be specialized for each architecture. As we show, all of these approaches critically depend on their software framework for discovery, execution, scheduling, and data orchestration. To address this challenge, we believe that a more agile and proactive software framework is essential to increase performance portability and improve user productivity. To this end, we have designed and implemented IRIS: a performance-portable framework for cross-platform heterogeneous computing. IRIS can discover available resources, manage multiple diverse programming platforms (e.g., CUDA, Hexagon, HIP, Level Zero, OpenCL, OpenMP) simultaneously in the same execution, respect data dependencies, orchestrate data movement proactively, and provide for user-configurable scheduling. To simplify data movement, IRIS introduces a shared virtual device memory with relaxed consistency among different heterogeneous devices. IRIS also adds an automatic kernel workload partitioning technique using the polyhedral model so that it can resize kernels for a wide range of devices. Our evaluation on three architectures, ranging from Qualcomm Snapdragon to a Summit supercomputer node, shows that IRIS improves portability across a wide range of diverse heterogeneous architectures with negligible overhead.

关键词： Heterogeneous architectures runtime systems compilers programming models Heterogeneous architectures runtime systems compilers programming models

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On the Exploitation of Loop-level Parallelism in Embedded Applications

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ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS 2009年第2期8卷 1–34页

作者： Kejariwal, Arun Veidenbaum, Alexander V. Nicolau, Alexandru Girkar, Milind Tian, Xinmin Saito, Hideki Univ Calif Irvine Ctr Embedded Comp Syst Irvine CA 92697 USA Intel Corp Intel Compiler Lab Santa Clara CA 95051 USA

Advances in the silicon technology have enabled increasing support for hardware parallelism in embedded processors. Vector units, multiple processors/cores, multithreading, special-purpose accelerators such as DSPs or cryptographic engines, or a combination of the above have appeared in a number of processors. They serve to address the increasing performance requirements of modern embedded applications. To what extent the available hardware parallelism can be exploited is directly dependent on the amount of parallelism inherent in the given application and the congruence between the granularity of hardware and application parallelism. This paper discusses how loop-level parallelism in embedded applications can be exploited in hardware and software. Specifically, it evaluates the efficacy of automatic loop parallelization and the performance potential of different types of parallelism, viz., true thread-level parallelism (TLP), speculative thread-level parallelism and vector parallelism, when executing loops. Additionally, it discusses the interaction between parallelization and vectorization. Applications from both the industry-standard EEMBC (R)(1) 1.1, EEMBC 2.0 and the academic MiBench embedded benchmark suites are analyzed using the Intel (R)(2) C compiler. The results show the performance that can be achieved today on real hardware and using a production compiler, provide upper bounds on the performance potential of the different types of thread-level parallelism, and point out a number of issues that need to be addressed to improve performance. The latter include parallelization of libraries such as libc and design of parallel algorithms to allow maximal exploitation of parallelism. The results also point to the need for developing new benchmark suites more suitable to parallel compilation and execution.

关键词： Performance Measurement Multi-cores system-on-chip (Soc) programming models libraries multithreading vectorization thread-level speculation parallel loops

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OPERATING SYSTEMS RESEARCH FOR RECONFIGURABLE COMPUTING

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IEEE MICRO 2014年第1期34卷 55-59页

作者： Andrews, David Univ Arkansas Dept Comp Sci & Comp Engn Mullins Endowed Chair Comp Engn Fayetteville AR 72701 USA

THIS ARTICLE OVERVIEWS HOW THE RAPID CHANGES TO FIELD-PROGRAMMABLE GATE ARRAY (FPGA) DEVICES HAVE REFOCUSED OPERATING SYSTEMS RESEARCH WITHIN RECONFIGURABLE COMPUTING. WHERE THE GOAL WAS ONCE TO SIMPLY USE EXISTING OPERATING SYSTEMS, FPGA-BASED OS RESEARCH MAY NOW BE IN THE NEW POSITION OF HELPING DEFINE THE LOOK AND FEEL OF NEXT-GENERATION OPERATING SYSTEMS FOR EVOLVING CHIP-HETEROGENEOUS MULTIPROCESSOR SYSTEMS.

关键词： computer architecture Field programmable gate arrays FPGA heterogeneous multiprocessors multiprocessor systems on chip operating systems parallel and distributed systems Program processors programming models Real-time systems Reconfigurable architectures reconfigurable computing

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