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A Machine-Learning-Based Framework for Productive Locality Exploitation

IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2021年第6期32卷 1409-1424页

作者： Kayraklioglu, Engin Favry, Erwan El-Ghazawi, Tarek Hewlett Packard Enterprise Co San Jose CA 95002 USA Univ Paris Est F-77420 Champs Sur Marne France George Washington Univ Washington DC 20052 USA

Data locality is of extreme importance in programming distributed-memory architectures due to its implications on latency and energy consumption. Automated compiler and runtime system optimization studies have attempted to improve data locality exploitation without burdening the programmer. However, due to the difficulty of static code analysis, conservatism in compiler optimizations to avoid errors, and cost of dynamic analysis, the efficacy of automated optimizations is limited. Therefore, programmers need to spend significant effort in optimizing locality while creating applications for distributed memory parallel systems. We present a machine-learning based framework to automatically exploit locality in distributed memory applications. This framework takes application source whose time-critical blocks are marked by pragmas, and produces optimized source code that uses a regressor for efficient data movement. The regressor is trained with automatically-collected application profiles with very small input data sizes. We integrate our prototype in the Chapel language stack. In our experiments, we show that the Elastic Net model is the ideal regressor for our case and applications that utilize Elastic Net can perform very similarly to programmer-optimized versions. We also show that such regressors can be trained within few minutes on a cluster or within 30 minutes on a workstation, including data collection.

关键词： Optimization Reactive power programming Runtime Program processors Productivity Prefetching Data locality distributed memory programming models machine learning

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Enabling highly-scalable remote memory access programming with MPI-3 One Sided

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SCIENTIFIC programming 2014年第2期22卷 75-91页

作者： Gerstenberger, Robert Besta, Maciej Hoefler, Torsten ETH Dept Comp Sci CH-8092 Zurich Switzerland

Modern interconnects offer remote direct memory access (RDMA) features. Yet, most applications rely on explicit message passing for communications albeit their unwanted overheads. The MPI-3.0 standard defines a programming interface for exploiting RDMA networks directly, however, it's scalability and practicability has to be demonstrated in practice. In this work, we develop scalable bufferless protocols that implement the MPI-3.0 specification. Our protocols support scaling to millions of cores with negligible memory consumption while providing highest performance and minimal overheads. To arm programmers, we provide a spectrum of performance models for all critical functions and demonstrate the usability of our library and models with several application studies with up to half a million processes. We show that our design is comparable to, or better than UPC and Fortran Coarrays in terms of latency, bandwidth and message rate. We also demonstrate application performance improvements with comparable programming complexity.

关键词： programming systems programming models Remote Memory Access (RMA) Remote Direct Memory Access (RDMA) MPI-3 one sided communication

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Algorithm level power efficiency optimization for CPU-GPU processing element in data intensive SIMD/SPMD computing

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JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING 2011年第2期71卷 245-253页

作者： Ren, Da Qi Univ Tokyo Dept Comp Sci Bunkyo Ku Tokyo 1130033 Japan CREST JST Tokyo Japan

Power efficiency investigation has been required in each level of a High Performance Computing (HPC) system because of the increasing computation demands of scientific and engineering applications. Focusing on handling the critical design constraints in the software level that run beyond a parallel system composed of huge numbers of power-hungry components, we optimize HPC program design in order to achieve the best possible power performance on the target hardware platform. The power performance of a CUDA Processing Element (PE) is determined by both hardware factors including power features of each component including with CPU, GPU, main memory and PCI buses, and their interconnection architecture;and software factors including algorithm design and the character of executable instructions performed on it. In this paper, approaches to model and evaluate the power consumption of large scale SIMD computation by CUDA PEs on multi-core and GPU platforms are introduced. The model allows obtaining design characteristic values at the early programming stage, thus benefitting programmers by providing the necessary environment information for choosing the best power-efficient alternative. Based on the model, CPU Dynamic frequency scaling (DFS) can be applied on CUDA PE architecture that adjusts CPU frequency to enhance power efficiency of the entire PE without compromising its computing performance. The power model and power efficiency improvements of the new designs have been validated by measuring the new programs on the real GPU multiprocessing system. (C) 2010 Elsevier Inc. All rights reserved.

关键词： programming models Abstractions for data intensive computing Stream computing Green (power efficient) data intensive computing

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Integrating Transactions into the Data-Driven Multi-threading Model Using the TFlux Platform

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INTERNATIONAL JOURNAL OF PARALLEL programming 2016年第2期44卷 257-277页

作者： Diavastos, Andreas Trancoso, Pedro Lujan, Mikel Watson, Ian Univ Cyprus Dept Comp Sci POB 20537 CY-1678 Nicosia Cyprus Univ Manchester Sch Comp Sci Oxford Rd Manchester M13 9PL Lancs England

The introduction of multi-core processors has renewed the interest in programming models which can efficiently exploit general purpose parallelism. Data-Flow is one such model which has demonstrated significant potential in the past. However, it is generally associated with functional styles of programming which do not deal well with shared mutable state. There have been a number of attempts to introduce state into Data-Flow models and functional languages but none have proved able to maintain the simplicity and efficiency of pure Data-Flow parallelism. Transactional memory is a concurrency control mechanism that simplifies sharing data when developing parallel applications while at the same time promises to deliver affordable performance. In this paper we report our experience of integrating Transactional Memory and Data-Flow within the TFlux Platform. The ability of the Data-Flow model to expose large amounts of parallelism is maintained while Transactional Memory provides simplified sharing of mutable data in those circumstances where it is important to the expression of the program. The isolation property of transactions ensures that the exploitation of Data-Flow parallelism is not compromised. In this study we extend the TFlux platform, a Data-Driven Multi-threading implementation, to support transactions. We achieve this by proposing new pragmas that allow the programmer to specify transactions. In addition we extend the runtime functionality by integrating a software transactional memory library with TFlux. To test the proposed system, we ported two applications that require transactional memory: Random Counter and Labyrinth an implementation of Lee's parallel routing algorithm. Our results show good opportunities for scaling when using the integration of the two models.

关键词： programming models Future multi-cores Transactional Memory Data-Flow model Data-Driven Multi-threading

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Achieving programming model abstractions for reconfigurable computing

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2008年第1期16卷 34-44页

作者： Andrews, David Sass, Ron Anderson, Erik Agron, Jason Peck, Wesley Stevens, Jim Baijot, Fabrice Komp, Ed Univ Kansas Dept Elect Engn & Comp Sci Lawrence KS 66045 USA Univ N Carolina Dept Elect & Comp Engn Charlotte NC 28223 USA Univ So Calif Inst Informat Sci Los Angeles CA USA Univ Kansas Informat & Telecommun Technol Ctr Lawrence KS 66045 USA

This paper introduces hthreads, a unifying programming model for specifying application threads running within a hybrid computer processing unit (CPU)/field-programmable gate-array (FPGA) system. Presently accepted hybrid CPU/FPGA computational models-and access to these computational models via high level languages-focus on programming language extensions to increase accessibility and portability. However, this paper argues that new high-level programming models built on common software abstractions better address these goals. The hthreads system, in general, is unique within the reconfigurable computing community as it includes operating system and middleware layer abstractions that extend across the CPU/FPGA boundary. This enables all platform components to be abstracted into a unified multiprocessor architecture platform. Application programmers can then express their computations using threads specified from a single POSIX threads (pthreads) multithreaded application program and can then compile the threads to either run on the CPU or synthesize them to run within an FPGA. To enable this seamless framework, we have created the hardware thread interface (HWTI) component to provide an abstract, platform-independent compilation target for hardware-resident computations. The HWTI enables the use of standard thread communication and synchronization operations across the software/hardware boundary. Key operating system primitives have been mapped into hardware to provide threads running in both hardware and software uniform access to a set of sub-microsecond, minimal-jitter services. Migrating the operating system into hardware removes the potential bottleneck of routing all system service requests through a central CPU.

关键词： field-programmable gate arrays (FPGAs) operating systems programming models reconfigurable computing

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UNCERTAIN<T>: ABSTRACTIONS FOR UNCERTAIN HARDWARE AND SOFTWARE

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IEEE MICRO 2015年第3期35卷 132-143页

作者： Bornholt, James Mytkowicz, Todd McKinley, Kathryn S. Univ Washington Dept Comp Sci & Engn Seattle WA 98195 USA

BUILDING CORRECT, EFFICIENT SYSTEMS THAT REASON ABOUT THE APPROXIMATIONS PRODUCED BY SENSORS, MACHINE LEARNING, BIG DATA, HUMANS, AND APPROXIMATE HARDWARE AND SOFTWARE REQUIRES NEW STANDARDS AND ABSTRACTIONS. THE UNCERTAIN < T > SOFTWARE ABSTRACTION AIMS TO TACKLE THESE PERVASIVE CORRECTNESS, OPTIMIZATION, AND PROGRAMMABILITY PROBLEMS AND GUIDE HARDWARE AND SOFTWARE DESIGNERS IN PRODUCING ESTIMATES.

关键词： Big Data Hardware Software Codesign Learning Artificial Intelligence Uncertain Hardware Uncertain Software Sensors Machine Learning Big Data Software Abstraction Programmability Problems Global Positioning System Uncertainty Energy Efficiency Sensors programming Bayes Methods Probabilistic programming Uncertainty Estimates Energy Efficiency programming models Approximation Probabilistic programming

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A framework for argument-based task synchronization with automatic detection of dependencies

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PARALLEL COMPUTING 2013年第9期39卷 475-489页

作者： Gonzalez, Carlos H. Fraguela, Basilio B. Univ A Coruna Fac Informat Dept Elect & Sistemas La Coruna 15071 Spain

Synchronization in parallel applications can be achieved either implicitly or explicitly. Implicit synchronization is typical of programming environments that provide predefined, and often simple, patterns of parallelism such as data-parallel libraries and languages and skeletal operations. Nevertheless, more flexible approaches that allow to express arbitrary task-level parallel computations without a predefined structure request in turn that the user explicitly specifies the synchronization needed among the parallel tasks. In this paper we present a library-based approach that enables arbitrary patterns of parallelism with minimal effort for the user. Our proposal is the first generic approach to express parallelism we know of that requires neither explicit synchronizations nor a detail of the dependencies of the parallel tasks. Our strategy relies on expressing the parallel tasks as functions that convey their dependencies implicitly by means of their arguments. These function arguments are analyzed by our library, called DepSpawn, when a parallel task is spawned in order to enforce its dependencies. Our experiments indicate that DepSpawn is very competitive, both in terms of performance and programmability, with respect to a widespread high-level approach like OpenMP. (C) 2013 Elsevier B.V. All rights reserved.

关键词： Parallel programming Synchronization Out-of-order execution Libraries Dependencies programming models

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RESOURCE MANAGEMENT

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INTERNATIONAL JOURNAL OF HIGH PERFORMANCE COMPUTING APPLICATIONS 2009年第4期23卷 347-349页

作者： Maccabe, Arthur Falter, Hugo Kramer, William Oak Ridge Natl Lab Comp Sci & Math Div Oak Ridge TN USA Partec Cluster Competence Ctr San Jose CA USA Lawrence Berkeley Natl Lab NERSC Berkeley CA USA

Application scalability is directly related to the ability of the application developer to effectively use the resources provided by a computing system. As we start to address the development of exascale platforms, we must engage in a dialog to define the terms related to resource management. Approaches to resource management can be categorized in two dimensions: static/dynamic and explicit/implicit. The static/dynamic dimension refers to when resource management decisions are made: prior to program execution or during program execution. The implicit/explicit dimension refers to the object that implements the decision making: the tools that implement the programming environment or the application developer. The development of applications that can scale to the resources provided by an exascale system will require tools that allow programmers to move easily and seamlessly between these dimensions as they express resource management decisions.

关键词： scalable applications resource constrained applications programming models exascale resource management

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Optimal Selection of Airport Runway Configurations

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OPERATIONS RESEARCH 2011年第6期59卷 1407-1419页

作者： Bertsimas, Dimitris Frankovich, Michael Odoni, Amedeo MIT Ctr Operat Res Cambridge MA 02139 USA

We present a mixed integer programming (MIP) model to solve the problems of (i) selecting an airport's optimal sequence of runway configurations and (ii) determining the optimal balance of arrivals and departures to be served at any moment. These problems, the runway configuration management (RCM) problem and the arrival/departure runway balancing (ADRB) problem, respectively, are of critical importance in minimizing the delay of both in-flight and on-the-ground aircraft along with their associated costs. We show that under mild assumptions on the time required to change between configurations, large realistic problem instances can be solved within several seconds. Furthermore, as assumptions are relaxed, optimal solutions are still found within several minutes. Comparison with a sophisticated baseline heuristic reveals that in many cases the potential reduction in cost from using the method is significant and could be expected to be of the order of at least 10%. Finally, we present an extension of the MIP model to solve these two problems for a group of airports in a metropolitan area such as New York (metroplex), where operations at each airport within the metroplex might have an impact on operations at some of the other airports due to limitations in shared airspace.

关键词： Airport runways Arrivals and departures Mathematical intervals Optimal solutions Heuristics Integers Integer programming programming models Rationing

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SCHEDULING SUPPORT FOR CONCURRENCY AND PARALLELISM IN THE MACH OPERATING SYSTEM

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COMPUTER 1990年第5期23卷 35-43页

作者： BLACK, DL Carnegie Mellon Univ. Pittsburgh PA

The shared use of general-purpose uniprocessors is examined. Support for common uniform-memory-access architectures that have all memory equidistant from all processors in terms of access time is emphasized. This work is also applicable to non-uniform-memory-access machines, whose memory access times depend on the physical distance between the processor and the accessed memory, but it does not provide a complete solution to load-balancing problems for this class of machine. The discussion covers time-sharing scheduling, the Mach scheduler, programming models, scheduling concurrency support, processor allocation, and related work

关键词： Mach operating system Mach scheduler common uniform-memory-access architectures concurrency support general-purpose uniprocessors memory access times multiprogramming operating systems (computers) parallelism processor allocation programming models scheduling time-sharing scheduling

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