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Exascale Computing Trends: Adjusting to the "New Normal" for Computer Architecture

COMPUTING IN SCIENCE & ENGINEERING 2013年第6期15卷 16-26页

作者： Kogge, Peter Shalf, John Univ Notre Dame Notre Dame IN 46556 USA Univ Notre Dame Coll Engn Notre Dame IN 46556 USA Lawrence Berkeley Natl Lab Berkeley CA USA

We now have 20 years of data under our belt about the performance of supercomputers against at least a single floating-point benchmark from dense linear algebra. Until about 2004, a single model of parallel programmin... 详细信息

关键词： Computer Architecture Market Research Transistors programming Computational Modeling Memory Management Systems Engineering And Theory programming models Computer Architecture Market Research Transistors programming Computational Modeling Memory Management Systems Engineering And Theory Scientific Computing Exascale HPC Computer Architecture

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C plus plus Support and Applications for Embedded Multicore DSP Systems

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JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2014年第2期75卷 109-122页

作者： Kuan, Chi-Bang Li, Jia-Jhe Chen, Chung-Kai Lee, Jenq-Kuen Natl Tsing Hua Univ Dept Comp Sci Hsinchu 30043 Taiwan Realtek Semicond Corp Hsinchu Taiwan

In recent years embedded systems have entered the multicore era. As the number of cores keeps growing in embedded systems, it becomes more important to provide programming support which considers embedded system constraints and in the meanwhile helps utilize multicore systems. So far though C still dominates embedded programming, C++ is gaining in importance in parallel programming. It is promising to support C++ for embedded multicore systems. However, embedded systems usually have tight resource budgets, and C++ is commonly considered having huge code size that embedded systems can not afford. Therefore, in this paper we investigate the code size requirement of a C++ library and propose a layered design to provide a code size aware library support. On the other hand, to utilize embedded multicore systems, we employ C++ linguistic features to facilitate embedded multicore programming. With C++, we incorporate high-level abstractions and design patterns into the programming support to enhance low-level programming APIs that can be used to exploit DSPs, SIMD instructions, and DMAs on embedded multicore systems. At last, we evaluate our C++ support with a Blur and a JPEG program. Our result on a dual-DSP platform shows that we can obtain speedups of 3.32 and 3.09 for the Blur and JPEG program, respectively.

关键词： Embedded multicore systems C plus plus library programming models Parallel design patterns

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Evolution of a minimal parallel programming model

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INTERNATIONAL JOURNAL OF HIGH PERFORMANCE COMPUTING APPLICATIONS 2018年第1期32卷 4-13页

作者： Lusk, Ewing Butler, Ralph Pieper, Steven C. Argonne Natl Lab Math & Comp Sci Div 9700 S Cass Ave Argonne IL 60439 USA Argonne Natl Lab Div Phys 9700 S Cass Ave Argonne IL 60439 USA Middle Tennessee State Univ Comp Sci Murfreesboro TN 37130 USA

We take a historical approach to our presentation of self-scheduled task parallelism, a programming model with its origins in early irregular and nondeterministic computations encountered in automated theorem proving and logic programming. We show how an extremely simple task model has evolved into a system, asynchronous dynamic load balancing (ADLB), and a scalable implementation capable of supporting sophisticated applications on today's (and tomorrow's) largest supercomputers;and we illustrate the use of ADLB with a Green's function Monte Carlo application, a modern, mature nuclear physics code in production use. Our lesson is that by surrendering a certain amount of generality and thus applicability, a minimal programming model (in terms of its basic concepts and the size of its application programmer interface) can achieve extreme scalability without introducing complexity.

关键词： Parallel computing programming models load balancing automated theorem proving nuclear physics

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Risk-Averse Two-Stage Stochastic Linear programming: Modeling and Decomposition

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OPERATIONS RESEARCH 2011年第1期59卷 125-132页

作者： Miller, Naomi Ruszczynski, Andrzej Rutgers State Univ RUTCOR Piscataway NJ 08854 USA Rutgers State Univ Dept Management Sci & Informat Syst Piscataway NJ 08854 USA

We formulate a risk-averse two-stage stochastic linear programming problem in which unresolved uncertainty remains after the second stage. The objective function is formulated as a composition of conditional risk measures. We analyze properties of the problem and derive necessary and sufficient optimality conditions. Next, we construct a new decomposition method for solving the problem that exploits the composite structure of the objective function. We illustrate its performance on a portfolio optimization problem.

关键词： Linear programming Risk aversion Mathematical vectors Stochastic models Decomposition methods Financial risk Mathematical functions programming models Modeling

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High performance remote memory access communication: The ARMCI approach

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INTERNATIONAL JOURNAL OF HIGH PERFORMANCE COMPUTING APPLICATIONS 2006年第2期20卷 233-253页

作者： Nieplocha, J. Tipparaju, V. Krishnan, M. Panda, D. K. Pacific NW Natl Lab Computat Sci & Math Dept Richland WA 99352 USA Ohio State Univ Columbus OH 43210 USA

This paper describes the Aggregate Remote Memory Copy Interface (ARMCI), a portable high performance remote memory access communication interface, developed originally under the U.S. Department of Energy (DOE) Advanced Computational Testing and Simulation Toolkit project and currently used and advanced as a part of the run-time layer of the DOE project, programming models for Scalable Parallel Computing. The paper discusses the model, addresses challenges of portable implementations, and demonstrates that ARMCI delivers high performance on a variety of platforms. Special emphasis is placed on the latency hiding mechanisms and ability to optimize noncontiguous data transfers.

关键词： remote memory access one-sided communication programming models ARMCI high performance networks

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Aligning the representation and reality of computation with asynchronous logic automata

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COMPUTING 2011年第2-4期93卷 91-102页

作者： Gershenfeld, Neil MIT Ctr Bits & Atoms Cambridge MA 02139 USA

There are many models of computation, but they all share the same underlying laws of physics. Software can represent physical quantities, but is not itself written with physical units. This division in representations, dating back to the origins of computer science, imposes increasingly heroic measures to maintain the fiction that software is executed in a virtual world. I consider instead an alternative approach, representing computation so that hardware and software are aligned at all levels of description. By abstracting physics with asynchronous logic automata I show that this alignment can not only improve scalability, portability, and performance, but also simplify programming and expand applications.

关键词： Logic automata Spatial computing programming models Parallel computing Computer architecture

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Interaction-Oriented Software Engineering: programming abstractions for autonomy and decentralization

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AI COMMUNICATIONS 2022年第4期35卷 381-391页

作者： Chopra, Amit K. Univ Lancaster Sch Comp & Commun Lancaster England

We review the main ideas and elements of Interaction-Oriented Software Engineering (IOSE), a program of research that we have pursued for the last two decades, a span of time in which it has grown from philosophy to practical programming abstractions. What distinguishes IOSE from any other program of research is its emphasis on supporting autonomy by modeling the meaning of communication and using that as the basis for engineering decentralized sociotechnical systems. Meaning sounds esoteric but is the basis for practical decision making and a holy grail for the field of distributed systems. We describe our contributions so far, directions for research, and the potential for broad impact on computing.

关键词： Autonomy decentralization meaning sociotechnical systems multiagent systems protocols norms programming models causality

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TH-1: China's first petaflop supercomputer

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中国计算机科学前沿 2010年第4期4卷 445-455页

作者： Xuejun YANG Xiangke LIAO Weixia XU Junqiang SONG Qingfeng HU Jinshu SU Liquan XIAO Kai LU Qiang DOU Juping JIANG Canqun YANG School of Computer Science National University of Defense TechnologyChangsha 410073China

In recent years, heterogeneous systems and cooperative computing have become popular research directions in the field of high performance *** fast scaling of the size of high performance computer systems, problems such as power consumption and reliability come to the forefront. The aim of high performance computing has thus shifred from merely seeking peak performance to comprehensively pursuing high efficiency, which takes into consideration many factors including performance, cost, power, reliability and so on. A heterogeneous computing system consisting of general-purpose CPU(s) and special-purpose accelerator(s) features high performance, lower power consumption and low cost, etc. Hence, it has already become the mainstream in the field of high performance computing. However, such systems still face many challenges and problems, for example, programmability and reliability. In this paper, we firstly analyze the main challenges facingheterogeneous computing systems. Then, we introduce the architecture of the first petafiop computing system in China, the Tianhe-1 (TH-1) heterogeneous system,including its hardware/software interface and interconnect network. During development of the TH-1 system, several challenges were encountered; research into the solutions of these challenges is subsequently presented.

关键词： heterogeneous systems cooperative computing Tianhe-1 (TH-1) system load balancing programming models low power consumption fault tolerance

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REDUCED INTERPROCESSOR-COMMUNICATION ARCHITECTURE AND ITS IMPLEMENTATION ON EM-4

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PARALLEL COMPUTING 1995年第5期21卷 753-769页

作者： SAKAI, S KODAMA, Y SATO, M SHAW, A MATSUOKA, H HIRONO, H OKAMOTO, K YOKOTA, T ELECTROTECH LAB DIV COMP SCITSUKUBAIBARAKI 305JAPAN MIT COMP SCI LABCAMBRIDGEMA 02139

One of the most significant issues in building general purpose massively parallel computers is the integration of computation and communication in an efficient and cost-effective manner. This paper presents a way of integrating computation and communication from the viewpoint of the processor architecture. Two statements will be presented and examined: (1) computation and communication should be tightly coupled and their operation should be highly overlapped;and (2) communication structure should be efficient and simple, i.e. turnaround from data input to execution should be as short as possible using a simplified message handling mechanism, Briefly we can say 'Fuse communication and computation, then reduce the fused structure as simple and efficient as possible'. The fused structure is called RICA, Reduced Interprocessor-Communication Architecture, in this paper, The word 'Reduced' here means the simplified structure of message handling, invocation of a new thread, computation and message generation. Based on the RICA design principles, the authors have developed the EM-series parallel computers, EM-4, EM-X and EM-5. This paper concentrates on the architecture and implementation of EM-4, whose first prototype has been fully operational since April 1990. The communication performance of EM-4 is comparable with its computation performance. These two primitives are efficiently and simply fused within the EM-4 architecture, i.e. a simple fused pipeline which performs message handling, instruction execution and packet output: message-handling time is two RISC clocks which is independent of executing processor instructions. This pipeline naturally includes a sequential RISC pipeline for executing local operations. Secondly this paper evaluates RICA by implementing on EM-4 several programming models generally considered 'effective' or 'promising'. The multi-threaded model, message passing model and data-parallel model have been implemented and a shared-memory model is be

关键词： MASSIVELY PARALLEL COMPUTERS INTERPROCESSOR COMMUNICATION EM-4 PROTOTYPE RICA (REDUCED INTERPROCESSOR COMMUNICATION ARCHITECTURE) programming models

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ADDING FAULT-TOLERANT TRANSACTION PROCESSING TO LINDA

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SOFTWARE-PRACTICE & EXPERIENCE 1994年第5期24卷 449-466页

作者： CANNON, SR DUNN, D Department of Computer Science Utah State University Logan Utah 84322–4205 U.S.A.

To simplify the difficult task of writing fault-tolerant parallel software, we implemented extensions to the basic functionality of the LINDA or tuple-space programming model. Our approach implements a mechanism of transaction processing to ensure that tuples are properly handled in the event of a node or communications failure. If a process retrieving a tuple fails to complete processing or a tuple posting or retrieval message is lost, the system is automatically rolled back to a previous stable state. Processing failures and lost messages are detected by time-out alarms. Roll-back is accomplished by reposting pertinent tuples. Intermediate tuples produced during partial processing are not committed or made available until a process completes. In the absence of faults, system overhead is low. The fault-tolerance mechanism is implemented at the system level and requires little programmer effort or expertise. Two implementations of the model are discussed, one using a UNIX network of workstations and one using a Transputer network. Data measuring model overhead and some aspects of system performance in the presence of faults is presented for an example system.

关键词： FAULT TOLERANCE LINDA RELIABILITY programming models

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