检索结果-内蒙古大学图书馆

A CHANCE-CONSTRAINED GOAL programming-MODEL FOR CAPITAL-BUDGETING

JOURNAL OF THE OPERATIONAL RESEARCH SOCIETY 1982年第7期33卷 635-638页

作者： DE, PK ACHARYA, D SAHU, KC Industrial Management Centre Indian Institute of Technology Kharagpur India

A chance-constrained formulation is presented for a zero-one goal programming problem whose coefficients in the technological matrix are stochastic. The model is presented with a numerical example. A capital budgeting... 详细信息

关键词： Goal programming Capital budgeting Determinism programming models Working capital Net present value Approximation Input data Modeling Coefficients

来源：评论

学校读者我要写书评

暂无评论

MAXIMIN programming, FUZZY LINEAR-programming AND MULTI-CRITERIA DECISION-MAKING

引用

JOURNAL OF THE OPERATIONAL RESEARCH SOCIETY 1980年第3期31卷 263-267页

作者： DYSON, RG University of Warwick

Mathematical programming models present an approach to solving multicriteria decision problems. This paper compares two such models. One based on fuzzy set theory, the other relying on utility functions and the maximin decision criteria. The two models have identical form. The paper also illustrates the relationship between fuzzy set theory and multi-criteria decision making.

关键词： Utility functions Maximin Fuzzy sets Objective functions Membership functions Linear programming Fuzzy set theory Decision making Ascriptions programming models

来源：评论

学校读者我要写书评

暂无评论

Extending OpenMP to Survive the Heterogeneous Multi-Core Era

引用

INTERNATIONAL JOURNAL OF PARALLEL programming 2010年第5-6期38卷 440-459页

作者： Ayguade, Eduard Badia, Rosa M. Bellens, Pieter Cabrera, Daniel Duran, Alejandro Ferrer, Roger Gonzalez, Marc Igual, Francisco Jimenez-Gonzalez, Daniel Labarta, Jesus Martinell, Luis Martorell, Xavier Mayo, Rafael Perez, Josep M. Planas, Judit Quintana-Orti, Enrique S. Barcelona Supercomp Ctr Ctr Nacl Supercomputac BSC CNS Barcelona 08034 Spain Univ Politecn Cataluna Depto Arquitectura Comp ES-08034 Barcelona Spain Spanish Natl Res Council CSIC Artificial Intelligence Res Inst Madrid Spain UJI Depto Ingn & Ciencia Comp Castellon de La Plana 12071 Spain

This paper advances the state-of-the-art in programming models for exploiting task-level parallelism on heterogeneous many-core systems, presenting a number of extensions to the OpenMP language inspired in the StarSs programming model. The proposed extensions allow the programmer to write portable code easily for a number of different platforms, relieving him/her from developing the specific code to off-load tasks to the accelerators and the synchronization of tasks. Our results obtained from the StarSs instantiations for SMPs, the Cell, and GPUs report reasonable parallel performance. However, the real impact of our approach in is the productivity gains it yields for the programmer.

关键词： Parallel computing programming models Runtime systems Task-level parallelism Multi-core processors Hardware accelerators Heterogeneous computing

来源：评论

学校读者我要写书评

暂无评论

What Scalable Programs Need from Transactional Memory 17

What Scalable Programs Need from Transactional Memory

引用

22nd ACM International Conference on Architectural Support for programming Languages and Operating Systems (ASPLOS)

作者： Nguyen, Donald Pingali, Keshav Synthace Ltd London England Univ Texas Austin Austin TX 78712 USA

ISBN: (纸本)9781450344654

Transactional memory (TM) has been the focus of numerous studies, and it is supported in processors such as the IBM Blue Gene/Q and Intel Haswell. Many studies have used the STAMP benchmark suite to evaluate their designs. However, the speedups obtained for the STAMP benchmarks on all TM systems we know of are quite limited;for example, with 64 threads on the IBM Blue Gene/Q, we observe a median speedup of 1.4X using the Blue Gene/Q hardware transactional memory (HTM), and a median speedup of 4.1X using a software transactional memory (STM). What limits the performance of these benchmarks on TMs? In this paper, we argue that the problem lies with the programming model and data structures used to write them. To make this point, we articulate two principles that we believe must be embodied in any scalable program and argue that STAMP programs violate both of them. By modifying the STAMP programs to satisfy both principles, we produce a new set of programs that we call the Stampede suite. Its median speedup on the Blue Gene/Q is 8.0X when using an STM. The two principles also permit us to simplify the TM design. Using this new STM with the Stampede benchmarks, we obtain a median speedup of 17.7X with 64 threads on the Blue Gene/Q and 13.2X with 32 threads on an Intel Westmere system. These results suggest that HTM and STM designs will benefit if more attention is paid to the division of labor between application programs, systems software, and hardware.

关键词： transactions transactional memory programming models scalability STAMP benchmarks Stampede benchmarks

来源：评论

学校读者我要写书评

暂无评论

Parallel programming Patterns for Multi-Processor SoC: Application to Video Processing

引用

ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS 2013年第1S期12卷 1–25页

作者： Paulin, Pierre G. Oezcan, Ali Erdem Gagne, Vincent Lavigueur, Bruno Benny, Olivier STMicroelect Canada Inc 16 Fitzgerald RdSuite 100 Ottawa ON K2H 8R6 Canada

Efficient, scalable and productive parallel programming is a major challenge for exploiting the future multiprocessor SoC platforms. This article presents the MultiFlex programming environment which has been developed to address this challenge. It is targeted for use on Platform 2012, a scalable multi-processor fabric. The MultiFlex environment supports high-level simulation, iterative platform mapping, and includes tools for programming model aware debug, trace, visualization and analysis. This article focuses on the two classes of programming abstractions supported in MultiFlex. The first is a set of Parallel programming Patterns (PPP) which offer a rich set of programming abstractions for implementing efficient data-and task-level parallel applications. The second is a Reactive Task Management (RTM) abstraction, which offers a lightweight C-based API to support dynamic dispatching of small grain tasks on tightly coupled parallel processing resources. The use of the MultiFlex native programming model is illustrated through the capture and mapping of two representative video applications. The first is a high-quality rescaling (HQR) application on a multiprocessor platform. We present the details of the optimization process which was required for mapping the HQR application, for which the reference code requires 350 GIPS (giga instructions per second), onto a 16 processor cluster. Our results show that the parallel implementation using the PPP model offers almost linear acceleration with respect to the number of processing elements. The second application is a high-definition VC-1 decoder. For this application, we illustrate two different parallel programming model variants, one using PPPs, the other based on RTM. These two versions are mapped onto two variants of a homogeneous version of the Platform 2012 multi-core fabric.

关键词： Performance Experimentation Languages programming models components multi-core platform mapping

来源：评论

学校读者我要写书评

暂无评论

CONTRACTION MAPPINGS IN THEORY UNDERLYING DYNAMIC programming

引用

SIAM REVIEW 1967年第2期9卷 165-&页

作者： DENARDO, EV

来源：评论

学校读者我要写书评

暂无评论

Learn the Switches: Evolving FPGA NoCs with Stall-Free and Backpressure based Routers 30

Learn the Switches: Evolving FPGA NoCs with Stall-Free and B...

引用

30th International Conference on Field-Programmable Logic and Applications (FPL)

作者： Malik, Gurshaant Lang, Ian Elmor Pellizoni, Rodolfo Kapre, Nachiket Univ Waterloo Waterloo ON Canada

ISBN: (纸本)9781728199023

We can overcome the pessimism in worst-case routing latency analysis of timing-predictable Network-on-Chip (NoC) workloads by single digit factors through the use of a hybrid FPGA-optimized NoC. Timing-predictable FPGA-optimized NoCs such as HopliteBuf integrate stall-free FIFOs that are sized using offline, static analysis of a user-supplied flow pattern and rates. For certain bursty traffic and flow configurations, the static analysis delivers very large, sometimes infeasible, FIFO size bounds and large worst-case latency bounds. Alternatively, backpressure-based NoCs such as HopliteBP can operate with lower latencies for certain bursty flows. However, they suffer from severe pessimism in the analysis due to the effect of pipelining of packets and interleaving of flows at switch ports. As we show in this paper, a hybrid FPGA NoC that seamlessly composes both design styles on a per-switch basis, delivers the best of both worlds with improved feasibility (bounded operation), and tighter latency bounds. We select the NoC switch configuration though a novel evolutionary algorithm based on Maximum Likelihood Estimation (MLE). For synthetic (RANDOM, LOCAL) and real world (SpMV, Graph) workloads, we demonstrate approximate to 2-3x improvements in feasibility, approximate to 1-6.8x in worst-case latency while only requiring LUT cost approximate to 1-1.5x larger than the cheapest HopliteBuf solution. We also deploy and verify our NoC (PL) and MLE framework (PS) on a Pynq-Z1 to adapt and reconfigure NoC switches dynamically.

关键词： Architectures and Technology Methods and Tools programming models

来源：评论

学校读者我要写书评

暂无评论

Evaluating the Support of MTC Applications On Intel Xeon Phi Many-Core Accelerators

Evaluating the Support of MTC Applications On Intel Xeon Phi...

引用

IEEE International Conference on Cluster Computing (CLUSTER)

作者： Nookala, Poornima Dimitropoulos, Serapheim Stough, Karl Raicu, Ioan IIT Dept Comp Sci Chicago IL 60616 USA

ISBN: (纸本)9781467365987

As Many-Task Computing (MTC) is becoming common-place on clusters, grids, and supercomputers, research that aims to take advantage of the new advances in hardware for MTC workloads is becoming more relevant. A good example is the design of frameworks like GeMTC that incorporate general purpose GPU hardware to improve the concurrency of executing tasks. This work attempts to support MTC workloads on the Intel Xeon Phi accelerators. Our plan is to develop two frameworks that will achieve that goal. One based on OpenMP and the other one based on Intel's Symmetric Communication Interface (SCIF) provided for Many-Integrated Core (MIC) accelerators like the Xeon Phi. Both frameworks aim to provide the same interface as GeMTC, leveraging the integration efforts with the Swift parallel programming system. Our end-goal is to present how programming many-core computing processors can be made easier and more productive using OpenMP or SCIF, and enable the execution of MTC workloads hybrid accelerator-based systems.

关键词： Many-task computing Accelerators Intel Xeon Phi Coprocessor programming models Execution models

来源：评论

学校读者我要写书评

暂无评论

Performance study of multithreaded MPI and OpenMP tasking in a large scientific code 31

Performance study of multithreaded MPI and OpenMP tasking in...

引用

31st IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPS)

作者： Akhmetova, Dana Iakymchuk, Roman Ekeberg, Orjan Laure, Erwin KTH Royal Inst Technol Dept Computat Sci & Technol Stockholm Sweden

ISBN: (纸本)9780769561493

With a large variety and complexity of existing HPC machines and uncertainty regarding exact future Exascale hardware, it is not clear whether existing parallel scientific codes will perform well on future Exascale systems: they can be largely modified or even completely rewritten from scratch. Therefore, now it is important to ensure that software is ready for Exascale computing and will utilize all Exascale resources well. Many parallel programming models try to take into account all possible hardware features and nuances. However, the HPC community does not yet have a precise answer whether, for Exascale computing, there should be a natural evolution of existing models interoperable with each other or it should be a disruptive approach. Here, we focus on the first option, particularly on a practical assessment of how some parallel programming models can coexist with each other. This work describes two API combination scenarios on the example of iPIC3D [26], an implicit Particle-in-Cell code for space weather applications written in C++ and MPI plus OpenMP. The first scenario is to enable multiple OpenMP threads call MPI functions simultaneously, with no restrictions, using an MPI_THREAD_MULTIPLE thread safety level. The second scenario is to utilize the OpenMP tasking model on top of the first scenario. The paper reports a step-by-step methodology and experience with these API combinations in iPIC3D;provides the scaling tests for these implementations with up to 2048 physical cores;discusses occurred interoperability issues;and provides suggestions to programmers and scientists who may adopt these API combinations in their own codes.

关键词： API interoperability programming models MPI OpenMP tasks multithreading MPI_THREAD_MULTIPLE thread safety

来源：评论

学校读者我要写书评

暂无评论

IRIS: Exploring Performance Scaling of the Intelligent Runtime System and its Dynamic Scheduling Policies

IRIS: Exploring Performance Scaling of the Intelligent Runti...

引用

1st International Conference on Smart Energy Systems and Artificial Intelligence (SESAI)

作者： Johnston, Beau Miniskar, Narasinga Rao Young, Aaron Monil, Mohammad Alaul Haque Lee, Seyong Vetter, Jeffrey S. Oak Ridge Natl Lab Oak Ridge TN 37830 USA

ISBN: (纸本)9798350364613;9798350364606

High-Performance Computing is becoming increasingly heterogeneous, relying on a diverse mix of hardware to achieve good performance. Paradoxically, current drivers and frameworks for these devices typically require separate languages and implementations for each vendor. Furthermore, there are few tools and little support to schedule codes between these devices in a truly heterogeneous manner partly because of this fragmentation between vendors and the languages each supports. To overcome both limitations, the Intelligent Runtime System (IRIS) was developed. It allows a common task abstraction to automatically be shared among contemporary vendors and is run from a single host-side API. At runtime, IRIS queries the host system and registers which frameworks and drivers are available, these determine which kernels can be used by the scheduler-CPUs via OpenMP, Nvidia GPUs (CUDA), AMD CPUs (HIP), and Intel and Xilinx FPGAs with OpenCL. IRIS enables tasks to he scheduled to any heterogeneous device and resolves to the appropriate kernel binary at runtime it only uses the devices supported by the system on which it is run. IRIS supports single-task and graph-based expressions of dependencies of tasks. Additionally, IRIS features a range of dynamic scheduling policies, allowing complex chains of tasks and interactions to be executed, relieving the programmer/user from considering the system to assign tasks to devices optimally. This paper presents the peak performance attainable by IRIS over a range of systems each with different numbers and types of accelerator devices, it highlights the flexibility of IRIS since these devices are truly heterogeneous, relying on different back ends (drivers, frameworks, and languages) which historically required unique implementations to utilize them. We then use this peak performance as a baseline to compare increasingly complex chains of tasks (with increasingly complex task dependencies) and evaluate how IRIS copes. Finally, we consider

关键词： Execution Model Heterogeneous Computing Heterogeneous Systems High-Performance Computing Performance Portability programming models Runtime System Scheduling Policy Task Schedule

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：