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30th IEEE International Parallel and Distributed Processing Symposium (IPDPS)

作者： Booth, Joshua Dennis Kim, Kyungjoo Rajamanickam, Sivasankaran Sandia Natl Labs Ctr Res Comp POB 5800 Albuquerque NM 87185 USA

ISBN: (纸本)9781509036820

All many-core systems require fine-grained shared memory parallelism, however the most efficient way to extract such parallelism is far from trivial. Fine-grained parallel algorithms face various performance trade-offs related to tasking, accesses to global data-structures, and use of shared cache. While programming models provide high level abstractions, such as data and task parallelism, algorithmic choices still remain open on how to best implement irregular algorithms, such as sparse factorizations, while taking into account the trade-offs mentioned above. In this paper, we compare these performance trade-offs for task and data parallelism on different hardware architectures such as Intel Sandy Bridge, Intel Xeon Phi, and IBM Power8. We do this by comparing the scaling of a new task-parallel incomplete sparse Cholesky factorization called Tacho and a new data-parallel incomplete sparse LU factorization called Basker. Both solvers utilize Kokkos programming model and were developed within the ShyLU package of Trilinos. Using these two codes we demonstrate how high-level programming changes affect performance and overhead costs on multiple multi/many-core systems. We find that Kokkos is able to provide comparable performance with both parallel_for and task/futures on traditional x86 multicores. However, the choice of which high-level abstraction to use on many-core systems depends on both the architectures and input matrices.

关键词： Performance programming models Sparse Factorizations Sparse Linear Algebra

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Gears4Net-an Asynchronous programming Model

Gears4Net-an Asynchronous Programming Model

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38th International Conference on Parallel Processing

作者： Saternus, Martin Weis, Torben Holzapfel, Sebastian Wacker, Arno Univ Duisburg Essen Distributed Syst Grp D-47057 Duisburg Germany

ISBN: (纸本)9781424449231

We propose a programming model for scalable distributed applications. Our programming model aims at applications which have to handle a high number of concurrent network connections in parallel. Such load characteristics appear in Web 2.0 applications and in scientific network simulators. The problem originates at the I/O API provided by the operating system. Blocking I/O is easy to use, but in large scale scenarios the usage of threads and memory is excessive. Non-blocking I/O can theoretically reduce the resource consumption, but it is awkward to program. Our approach utilizes a special language feature found in Microsoft's C# and Python and combines the best of both worlds. programming is almost as easy as with blocking I/O and the resource usage is nearly optimal. Our solution is implemented on top of Microsoft .NET or Mono/Linux respectively and does not require any changes to the operating system, which is very valuable for its practical application.

关键词： Parallel programming programming models Concurrency

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Make Software Harder 15

Make Software Harder

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15th ACM International Conference on Computing Frontiers

作者： Bjornseth, Benjamin A. Meyer, Jan Christian Natvig, Lasse Norwegian Univ Sci & Technol Dept Comp Sci Trondheim Norway

ISBN: (纸本)9781450357616

programming models should ideally let programmers express their ideas directly and explicitly. No such models are available for expert programmers, authors of machine-specific code optimizations, whose ideas often exploit architectural details invisible even at the assembly language level. In this paper we call for filling this void, and define performance transparency to evaluate the extent to which a programming model accommodates the expert programmer use case. We propose a specific approach to attaining performance transparency: make software harder by exposing the key components of the target architecture. The opportunities and challenges this approach brings are discussed.

关键词： performance transparency programming models HPC

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A Domain-Specific Approach To Unifying The Many Dimensions of Context-Aware Home Service Development 4

A Domain-Specific Approach To Unifying The Many Dimensions o...

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IEEE SmartWorld, Ubiquitous Intelligence & Computing, Advanced & Trusted Computing, Scalable Computing & Communications, Cloud & Big Data Computing, Internet of People and Smart City Innovation (SmartWorld/SCALCOM/UIC/ATC/CBDCom/IOP/SCI)

作者： Volanschi, Nic Carteron, Adrien Consel, Charles INRIA Bordeaux France Bordeaux INP Bordeaux France

ISBN: (纸本)9781538693803

Developing context-aware homes involves a range of stakeholders, addressing many dimensions such as service design and development, infrastructure deployment, and maintenance. Such a variety of dimensions often translate into heterogeneous, low-level, silo-based processing of sensor data to extract context information. This paper analyzes a range of existing data processing layers in the domain of aging in place to identify key concepts and operations specific to context-aware processing. Based on this analysis, we introduce a context-aware, domain-specific language and its software architecture, which allow to put in synergy the stakeholders of a context-aware home by providing them with a unified approach to designing and developing services. Our approach offers context aware-specific abstractions and notations, within a data-centric and data-driven paradigm. We have validated our approach by applying it to an assisted living platform for aging in place, deployed in the home of 129 users. In particular, we used our domain-specific language to re-implement 53 existing services, originating from the stakeholders of the assisted living platform. These services were deployed and successfully tested for their effectiveness in performing the specific tasks of the stakeholders, such as detection of daily activities, user risk situations, or sensor failures.

关键词： context-aware domain-specific data-centric data-driven aging in place programming models

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Multi-processor SoC-based design methodologies using configurable and extensible processors

Multi-processor SoC-based design methodologies using configu...

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17th IEEE International Conference on Application-Specific Systems, Architectures and Processors

作者： Martin, Grant Tensilica Inc Santa Clara CA USA

The growing interest in multiprocessor system-on-chip (MPSoC) design, or 'multicore' processors, has resulted in some confusion between the various types of multiprocessor architectures and their suitability in different application spaces. In particular, there are clear differences between the general-purpose, symmetric multiprocessor (SMP) approaches, and the application-specific, asymmetric multiprocessor (AMP) architectures. Configurable and extensible processors are especially suited for the AMP approach, yet their flexibility means that new design methodologies and tools must be developed to allow effective utilisation of multiple instruction-set processors in a complex design. Configurable and extensible processors are especially well suited for data-intensive computational tasks, such as are found in many signal and image processing applications, including audio, video, and wireless and wired networking. A design methodology for such applications must pay careful attention to the right programming models, and dataflow styles of processing seem a natural fit to the application space. In this paper, we describe a design methodology, flow and tools for MPSoC design using configurable and extensible processors that is especially interesting for data-intensive dataflow style applications. Some of the issues involved in this design approach are used to highlight opportunities for ongoing research.

关键词： MPSoC multiprocessor system-on-chip configurable processor instruction-set extension electronic system-level design programming models dataflow

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Profiling and Debugging Support for the Kokkos programming Model

Profiling and Debugging Support for the Kokkos Programming M...

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International Supercomputing Conference (ISC) on High Performance

作者： Hammond, Simon D. Trott, Christian R. Ibanez, Daniel Sunderland, Daniel Sandia Natl Labs Ctr Comp Res Albuquerque NM 87123 USA

ISBN: (纸本)9783030024659;9783030024642

Supercomputing hardware is undergoing a period of significant change. In order to cope with the rapid pace of hardware and, in many cases, programming model innovation, we have developed the Kokkos programming Model - a C++-based abstraction that permits performance portability across diverse architectures. Our experience has shown that the abstractions developed can significantly frustrate debugging and profiling activities because they break expected code proximity and layout assumptions. In this paper we present the Kokkos Profiling interface, a lightweight, suite of hooks to which debugging and profiling tools can attach to gain deep insights into the execution and data structure behaviors of parallel programs written to the Kokkos interface.

关键词： Profiling Performance-portable programming models

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Combining Hard and Soft Constraints in Quantum Constraint-Satisfaction Systems

Combining Hard and Soft Constraints in Quantum Constraint-Sa...

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International Conference for High Performance Computing, Networking, Storage and Analysis (HPC)

作者： Wilson, Ellis Mueller, Frank Pakin, Scott North Carolina State Univ Raleigh NC 27695 USA Los Alamos Natl Lab Los Alamos NM 87545 USA

ISBN: (纸本)9781665454445

This work presents a generalization of NchooseK, a constraint satisfaction system designed to target both quantum circuit devices and quantum annealing devices. Previously, NchooseK supported only hard constraints, which made it suitable for expressing problems in NP (e.g., 3-SAT) but not NP-hard problems (e.g., minimum vertex cover). In this paper we show how support for soft constraints can be added to the model and implementation, broadening the classes of problems that can be expressed elegantly in NchooseK without sacrificing portability across different quantum devices. Through a set of examples, we argue that this enhanced version of NchooseK enables problems to be expressed in a more concise, less error-prone manner than if these problems were encoded manually for quantum execution. We include an empirical evaluation of performance, scalability, and fidelity on both a large IBM Q system and a large D-Wave system.

关键词： circuit-model quantum computing quantum annealing programming models

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A MICRO-ECONOMETRIC MODEL OF CAPITAL UTILIZATION AND RETIREMENT - THE CASE OF THE UNITED-STATES CEMENT INDUSTRY

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REVIEW OF ECONOMIC STUDIES 1992年第2期59卷 277-297页

作者： DAS, S INDIANA UNIV BLOOMINGTONIN 47401 USA

The paper presents a micro-econometric model of capital utilization and retirement. Estimates of a firm's discrete decision problem with regard to an existing piece of capital-whether to operate, hold idle or retire it-are obtained, in the context of the U.S. cement industry, by solving a discrete-choice stochastic dynamic programming model. The estimates are then used to simulate the effects of product and input price changes, and changes in the size and age of a cement kiln on a firm's propensity to operate, hold idle and retire a kiln.

关键词： Kilns Cements Age Dynamic modeling Average variable cost Fixed costs Mathematical independent variables Dynamic programming programming models Maximum likelihood estimation

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Correct translation of data parallel assignment onto array processors

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Formal Aspects of Computing 1994年第4期6卷 417-439页

作者： Wray, J.P. Stewart, A. Department of Computer Science The Queen's University of Belfast Belfast BT7 1NN University Road United Kingdom

Two models of computation which are suitable for the description of parallel scientific calculations on large data structures are presented. Data parallel assignment is a construct which may be used to specify the application of a set of order independent fine grained operations to a regular data structure. It is formulated in a machine independent way and, consequently, is suitable for implementation on a range of novel parallel architectures. An operational model of data parallel computation is provided by specifying a model array processor. The specification captures the essential features of the class of array processors and it may be instantiated in order to define a particular machine. A formal operational semantics of data parallel assignment is given for the model array processor. The translation mechanism is shown to be correct. The exercise clarifies some of the issues in deciding whether or not it is feasible to translate data parallel assignment directly onto array processor architectures. © 1994 BCS.

关键词： Architectural models Array assignment Array processor Correct translation Data parallelism programming models

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Wafer-Scale Fast Fourier Transforms 23

Wafer-Scale Fast Fourier Transforms

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37th ACM International Conference on Supercomputing (ACM ICS)

作者： Orenes-Vera, Marcelo Sharapov, Ilya Schreiber, Robert Jacquelin, Mathias Vandermersch, Philippe Chetlur, Sharan Princeton Univ Princeton NJ 08544 USA Cerebras Syst Sunnyvale CA USA Princeton Univ Princeton NJ 08544 USA Cerebras Syst Sunnyvale CA USA

ISBN: (纸本)9798400700569

We have implemented fast Fourier transforms for one, two, and three-dimensional arrays on the Cerebras CS-2, a system whose memory and processing elements reside on a single silicon wafer. The wafer-scale engine (WSE) encompasses a two-dimensional mesh of roughly 850,000 processing elements (PEs) with fast local memory and equally fast nearest-neighbor interconnections. Our wafer-scale FFT (wsFFT) parallelizes a n(3) problem with up to n(2) PEs. At this point, a PE processes only a single vector of the 3D domain (known as a pencil) per superstep, where each of the three supersteps performs FFT along one of the three axes of the input array. Between supersteps, wsFFT redistributes (transposes) the data to bring all elements of each one-dimensional pencil being transformed into the memory of a single PE. Each redistribution causes an all-to-all communication along one of the mesh dimensions. Given the level of parallelism, the size of the messages transmitted between pairs of PEs can be as small as a single word. In theory, a mesh is not ideal for all-to-all communication due to its limited bisection bandwidth. However, the mesh interconnecting PEs on the WSE lies entirely on-wafer and achieves nearly peak bandwidth even with tiny messages. We analyze in detail computation and communication time, as well as the weak and strong scaling, using both FP16 and FP32 precision. With 32-bit arithmetic on the CS-2, we achieve 959 microseconds for 3D FFT of a 5123 complex input array using a 512 x 512 subgrid of the on-wafer PEs. This is the largest ever parallelization for this problem size and the first implementation that breaks the millisecond barrier.

关键词： FFT wafer-scale strong scaling massive parallelization explicit communication mesh network bandwidth programming models

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