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Parallel architecture support for high-speed protocol processing

MICROPROCESSORS AND MICROSYSTEMS 1997年第6期20卷 325-339页

作者： Chan, TS Gorton, I Computer and Systems Technology Laboratory School of Computer Science and Engineering University of New South Wales Sydney 2052 Australia

A rapid increase in the transmission bandwidth of optical networks has created a bottleneck in protocol processing at the host systems. This paper presents a high-performance transport protocol, HTPNET, that is designed to exploit the evolving characteristics of high-speed networks. Importantly, the highly parallel architecture of HTPNET provides a suitable platform for the parallel implementation of presentation processing, which incurs high computation overheads. A parallel architecture based on the T9000 transputer and C104 router technology has been designed to support high-speed protocol processing. A simulation of the architecture has been implemented and has demonstrated the advantage of exploiting a parallel architecture for protocol processing.

关键词： high-speed networks protocol processing parallel architecture transputer Occam

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Real-Time Guaranteed TDD protocol processing for Centralized Super Base Station Architecture

Real-Time Guaranteed TDD Protocol Processing for Centralized...

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IEEE Wireless Communications and Networking Conference (WCNC)

作者： Zhai, Guowei Tian, Lin Zhou, Yiqing Wang, Xiaodong Shi, Jinglin Chinese Acad Sci Inst Comp Technol Wireless Commun Res Ctr Beijing Key Lab Mobile Comp & Pervas Devices Beijing 100864 Peoples R China Columbia Univ Dept Elect Engn New York NY 10027 USA

ISBN: (纸本)9781479984060

The centralized radio access cellular network architecture with Super BS (CSBS) has been proposed to reduce high construction cost and energy consumption. In CSBS, the computing resource is centralized and can be flexibly allocated to different virtual BSs (VBS). In the general purpose platforms, the protocol processing of multiple VBS can be carried out in a single processor due to its high processing capability. However, using this organization, it is difficult to guarantee the real-time protocol processing in TDD systems. This paper firstly analyzes the requirement of real-time processing of TDD protocols. Then, a real-time guaranteed TDD protocol processing mechanism, dynamic adaptive organization mechanism (DAOM), is proposed, whose main idea is to carry out downlink protocol processing consecutively. Simulation results show that DAOM can guarantee the real-time protocol processing and keep a high computing resource efficiency at the same time.

关键词： virtual BS protocol processing real-time processing computing resource efficiency

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Parallelizing protocol processing on SMT processor efficiently: A FSM decomposition approach

Parallelizing protocol processing on SMT processor efficient...

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IEEE International Performance Computing and Communications Conference

作者： Zhang, Zhibin Guo, Li Fang, Binxing Chen, Xiaojun Chinese Acad Sci Inst Comp Technol Beijing 100080 Peoples R China Chinese Acad Sci Grad Univ Beijing 100039 Peoples R China

ISBN: (纸本)9781424411375

With the increase of network bandwidth, high performance protocol processing plays more and more important role in high speed network security. Recent studies show that current computer architecture advances and CPU performance improvements have limited impact on network protocol processing performance. Some studies find that in real SMT processor like Intel Xeon processor with Hyper-Threadings, the sharing resources (like cache) contention between threads can hurt the processing performance of network applications like servers or EDS. How to make protocol processing cope with the advances in computer architecture has been widely studied. In this paper, we put our focus on the processing performance of TCP automata phases, using execution based simulations to model the relationship between each phase performance and cache size, and then measuring the cache contention between threads. We find (1) The Load/Store units can be the bottleneck of protocol processing. (2) In connection establishing phase of TCP processing, cache contention between threads is more aggressive than any other phase. We also suggest a FSM decomposition based parallel processing approach to use sharing cache of SMT processors effectively.

关键词： SMT protocol processing FSM decomposition cache

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Service-Guaranteed Multi-Port Packet Memory for Parallel protocol processing Architecture 24

Service-Guaranteed Multi-Port Packet Memory for Parallel Pro...

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24th Euromicro International Conference on Parallel, Distributed, and Network-Based processing (PDP)

作者： Badawi, Mohammad Lu, Zhonghai Hemani, Ahmed KTH Royal Inst Technol Stockholm Sweden

ISBN: (纸本)9781467387767

Parallel processing architectures have been increasingly utilized due to their potential for improving performance and energy efficiency. Unfortunately, the anticipated improvement often suffers from a limitation caused by memory access latency and latency variation, which consequently impact Quality of Service (QoS). This paper presents a service guaranteed multi-port packet memory system to boost parallelism in protocol processing architectures. In this proposed memory system, all arriving packets are guaranteed a memory space, such that, a packet memory space can be allocated in a bounded number of cycles and each of its locations is accessible in a single cycle. We consider a real-time Voice Over Internet protocol (VOIP) call as a case-study to evaluate our service guaranteed memory system.

关键词： Multi-port Memory Packet-oriented Memory protocol processing service-guaranteed

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Low-latency and high bandwidth TCP/IP protocol processing through an integrated HW/SW approach

Low-latency and high bandwidth TCP/IP protocol processing th...

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IEEE INFOCOM Conference

作者： Ken Inoue Davide Pasetto Karol Lynch Massimiliano Meneghin Kay Muller John Sheehan IBM TJ Watson Research Center Yorktown Heights NY 10598 USA IBM Dublin Research Lab Ireland

ISBN: (纸本)9781467359443

Ultra low-latency networking is critical in many domains, such as high frequency trading and high performance computing (HPC), and highly desirable in many others such as VoIP and on-line gaming. In closed systems - such as those found in HPC - Infiniband, iWARP or RoCE are common choices as system architects have the opportunity to choose the best host configurations and networking fabric. However, the vast majority of networks are built upon Ethernet with nodes exchanging data using the standard TCP/IP stack. On such networks, achieving ultra low-latency while maintaining compatibility with a standard TCP/IP stack is crucial. To date, most efforts for low-latency packet transfers have focused on three main areas: (i) avoiding context switches, (ii) avoiding buffer copies, and (iii) off-loading protocol processing. This paper describes IBM PowerEN and its networking stack, showing that an integrated system design which treats Ethernet adapters as first class citizens that share the system bus with CPUs and memory, rather than as peripheral PCI Express attached devices, is a winning solution for achieving minimal latency. The work presents outstanding performance figures, including 1.30μs from wire to wire for UDP, usually the chosen protocol for latency sensitive applications, and excellent latency and bandwidth figures for the more complex TCP.

关键词： system buses protocol processing Ethernet networks High Performance Computing Networking central processing units Voice over Internet protocol Furnace conveyors high-bandwidth Latency

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Area-Efficient Dynamically Reconfigurable protocol-processing-Hardware for Access Network Communications SoC

Area-Efficient Dynamically Reconfigurable Protocol-Processin...

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2014 International Conference on Reconfigurable Computing and FAGAs

作者： Hatta, Saki Tanaka, Nobuyuki Shigematsu, Satoshi NTT Corp NTT Device Innovat Ctr Atsugi Kanagawa Japan

ISBN: (纸本)9781479959440

Our proposed architecture of dynamically reconfigurable hardware for protocol processing (DRHPP) provides flexibility with high area efficiency. It can be used for a communications system-on-a-chip (SoC) in access networks. The DRHPP enables the modification and addition of various functions for protocol processing. Our architecture consists of three types of cells. The optimized number of these types of cells for the intended protocol processing can be implemented for increasing cell utilization, which can decrease the total area. Additionally, the best granularity for the cell also contributes to a decrease of the total area. We implemented a protocol-processing circuit using DRHPP for protocol-frame parser processing. Implementation results show the proposed architecture improves flexibility with only a 33% area penalty in comparison with a hard-wired protocol-processing circuit.

关键词： reconfigurable protocol processing area-efficiency optimized cell communications SoC access networks

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Adaptive rate-controlled scheduling for multimedia applications

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IEEE-ACM TRANSACTIONS ON NETWORKING 1997年第4期5卷 475-488页

作者： Yau, DKY Lam, SS Dept. of Comput. Sci. Texas Univ. Austin TX USA

We present a framework for integrated scheduling of continuous media (CM) and other applications, The framework, called ARC scheduling, consists of a rate-controlled on-line CPU scheduler, an admission control interface, a monitoring module, and a rate adaptation interface, ARC scheduling allows threads to reserve CPU time for guaranteed progress, It provides firewall protection between threads such that the progress guarantee to a thread is independent of how other threads actually make scheduling requests, Rate adaptation allows a CM application to adapt its rate to changes in its execution environment, We have implemented the framework as an extension to Solaris 2.3, We present experimental results which show that ARC scheduling is highly effective for integrated scheduling of CM and other applications in a general purpose workstation environment, ARC scheduling is a key component of an end system architecture we have designed and implemented to support networking with quality of service guarantees, In particular, it enables protocol threads to make guaranteed progress.

关键词： adaptive rate control continuous media CPU scheduling end system support protocol processing QoS guarantee rate reservation

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ASN.1 protocol specification for use with arbitrary encoding schemes

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IEEE-ACM TRANSACTIONS ON NETWORKING 1997年第4期5卷 502-513页

作者： Tantiprasut, D Neil, J Farrell, C Sch. of Comput. Sci. Curtin Univ. of Technol. Perth WA Australia

Abstract Syntax Notation One (ASN.1) is a language for describing structured information, It is generally used in the specification of communications protocols. To date, it has primarily been used in the specification of OSI application layer protocols and protocols which use Basic Encoding Rules (BER) and its derivatives as encoding schemes, While it is difficult to understand why ASN.1 has not received more widespread use for protocol specification, one possible explanation is its perceived reliance on BER and its derivatives as encoding schemes, This work attempts to address this misconception by providing mappings for ASN.1 constructs directly onto encoding schemes other than BER. By harnessing the techniques described, ASN.1 can be used to describe new and existing protocols regardless of their encoding scheme. The effectiveness of our techniques is demonstrated using a protocol analyzer (sometimes called a packet analyzer), protocol analyzers decode and display protocol data units (PDU's), A major limitation of many protocol analyzers is their inability to dynamically incorporate new and proprietary PDU's, A ''proof of concept'' for the solutions suggested in this paper is provided via a protocol analyzer capable of processing protocols directly from an ASN.1 specification.

关键词： protocols Abstract Data Types Specification Languages Formal Specification Encoding Computer Networks Open Systems ASN 1 protocol Specification Encoding Abstract Syntax Notation One Structured Information Communications protocols OSI Application Layer protocols Basic Encoding Rules protocol Analyzer Packet Analyzer protocol Data Units protocol processing Computer Networks Specification Language protocols Encoding Bit Error Rate Specification Languages Open Systems Formal Specifications Decoding Displays Computer Networks Software Engineering

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A high-speed network interface for distributed-memory systems: Architecture and applications

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ACM TRANSACTIONS ON COMPUTER SYSTEMS 1997年第1期15卷 75-109页

作者： Steenkiste, P Carnegie Mellon Univ. Pittsburgh PA

Distributed-memory systems have traditionally had great difficulty performing network I/O at rates proportional to their computational power. The problem is that the network interface has to support network I/O for a supercomputer, using computational and memory bandwidth resources similar to those of a workstation. As a result, the network interface becomes a bottleneck. In this article we present an I/O architecture that addresses these problems and supports high-speed network I/O on distributed-memory systems. The key to good performance is to partition the work appropriately between the system and the network interface. Some communication tasks are performed on the distributed-memory parallel system, since it is more powerful and less likely to become a bottleneck than the network interface. Tasks that do not parallelize well are performed on the network interface, and hardware support is provided for the most time-critical operations. This architecture has been implemented for the iWarp distributed-memory system and has been used by a number of applications. We describe this implementation, present performance results, and use application examples to validate the main features of the I/O architecture.

关键词： application-managed I/O data reshuffling distributed-memory systems I/O architecture network interface outboard buffering protocol processing resource management

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A SURVEY OF LIGHTWEIGHT TRANSPORT protocolS FOR HIGH-SPEED NETWORKS

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IEEE TRANSACTIONS ON COMMUNICATIONS 1990年第11期38卷 2025-2037页

作者： DOERINGER, WA DYKEMAN, D KAISERSWERTH, M MEISTER, BW RUDIN, H WILLIAMSON, R Zurich Research Laboratory IBM Research Division Ruschlikon Switzerland

Made possible by progress in fiber-optic and VLSI technologies, networks offering increasing transmission capacity at decreasing error rates are becoming available. New applications would benefit from this bandwidth but software protocol processing rates have not kept up with available raw transmission speed. We present a comparative survey of techniques used at the transport layer in eight representative protocols, most of which were designed to improve the protocol processing rate. The protocols are the relevant portions of the APPN, Datakit, Delta-t, NETBLT, OSI/TP4, TCP, VMTP, and XTP architectures. We then go on to discuss which of those techniques seem the most promising to us. An extensive list of references is included.

关键词： end-to-end transfer High-speed networks error handling transport protocols End of Transmission transport layer protocol processing

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