An algorithm is developed for the generation of pulsewidth modulated signals using Dual Reference modulation (DRM) for a five level inverter used in Photovoltaic (PV) based electrical power generation systems. With f...
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ISBN:
(数字)9798331507671
ISBN:
(纸本)9798331507688
An algorithm is developed for the generation of pulsewidth modulated signals using Dual Reference modulation (DRM) for a five level inverter used in Photovoltaic (PV) based electrical power generation systems. With five level inverters offering a significant edge over the conventional inverters along with an efficient algorithm that is developed in this work, it becomes extremely simple and viable for implementation. This algorithm is made to be compatible with Arduino to facilitate easier implementation while also focusing on reducing the Total Harmonic Distortions (THD) below what conventional five level inverters offer. The developed algorithm to generate PWM signals uses DRM technique that employs one carrier signal and two reference signals. Extensive simulations have been carried out in Simulink. The five level inverter with a reduced number of switches is fabricated and tested on an experimental setup. Experiments have been carried out on the developed inverter and its performance is analyzed considering voltage, current and THD on the output for different modulation indices and switching frequencies. For a switching frequency of 2 kHz and a modulation index of 1, THD obtained with the five level inverter is around $\mathbf{2 0 \%}$ . It is inferred that the implemented PWM algorithm on the inverter produced five levels on the output with an easier implementation algorithm, while employing a reduced number of switches.
Effective neutral-point balancing in a neutral-point-clamped inverter can yield substantial benefits, including cost reduction and efficiency improvement for the system. This article proposes a new piecewise pulse-wid...
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Effective neutral-point balancing in a neutral-point-clamped inverter can yield substantial benefits, including cost reduction and efficiency improvement for the system. This article proposes a new piecewise pulse-widthmodulation designed to reduce low-frequency oscillations of the neutral-point current without compromising the inverter power losses. The proposed piecewise modulation is simple to implement as it has one reference signal per phase. The performance of the proposed modulation is validated through comprehensive comparisons with alternative methods. The obtained simulation and experimental results demonstrate the effectiveness of the proposed piecewise modulation.
The voltage-fed quasi Z-source inverter (qZSI) is emerged as a promising solution for photovoltaic (PV) applications. This paper proposes a novel high-gain partition input union output dual impedance quasi Z-source in...
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Reduced component Multilevel inverters (RCMLIs) are gaining popularity in industrial applications due to their enhanced output quality when compared to traditional inverters. A critical parameter for evaluating this o...
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The harmonic elimination task of three-level neutral point clamped (3L-NPC) inverters is related to a complicated engineering optimization problem, which mainly involves constrained nonlinear transcendental equations ...
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ISBN:
(数字)9798331511241
ISBN:
(纸本)9798331511258
The harmonic elimination task of three-level neutral point clamped (3L-NPC) inverters is related to a complicated engineering optimization problem, which mainly involves constrained nonlinear transcendental equations with multiple solutions. In order to solve the problems of difficult initial value determination, slow convergence rates and susceptibility to local optima trapping in the process of using traditional numerical algorithms, This paper introduces a novel selective harmonic elimination pulse width modulation (SHEPWM) framework, enhanced by an adaptive restart genetic algorithm, to address the limitations of conventional optimization methods. By introducing the adaptive restart mechanism, the performance and robustness of the solution algorithm can be improved, so as to circumvent entrapment in local optima and secure the global optimum across the entire solution space. The simulation results show that there are divergent trends in the switching angles and the total harmonic distortion (THD) values of the output voltage obtained by the proposed method, but all of them can effectively eliminate the specified low-order harmonics. These findings verifies the practical applicability and solution diversity of the proposed method, as well as provides new ideas and methods for solving optimization problems in other engineering fields.
Reduced component Multilevel inverters (RCMLIs) are gaining popularity in industrial applications due to their enhanced output quality when compared to traditional inverters. A critical parameter for evaluating this o...
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ISBN:
(数字)9798331530402
ISBN:
(纸本)9798331530419
Reduced component Multilevel inverters (RCMLIs) are gaining popularity in industrial applications due to their enhanced output quality when compared to traditional inverters. A critical parameter for evaluating this output quality is Total Harmonic Distortion (THD). By selecting the appropriate pulse width modulation (PWM) techniques, it is possible to reduce THD effectively. High-frequency PWM schemes are particularly beneficial for switched capacitor MLIs, as they assist in managing capacitor inrush currents and enhancing capacitor lifespan. The newly proposed Variable Magnitude Multi-Carrier Level Shift PWM (PVMMCLSPWM) shows a notable decrease in THD compared to other high-frequency PWM methods available in the literature. Simulations of this technique have been conducted using a symmetrical nine-level MLI and benchmarked against the traditional Multi-Carrier Level Shift Phase Disposition PWM (MCLSPDPWM). The results of the comparative analysis highlight the enhanced performance of PVMMCLSPWM in minimizing THD.
A brushless DC motor that does not have the physical brushes and does its work through electronic commutation. It has low maintenance and a longer life span while being of high operating efficiency. Motor control meth...
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ISBN:
(数字)9798331512088
ISBN:
(纸本)9798331512095
A brushless DC motor that does not have the physical brushes and does its work through electronic commutation. It has low maintenance and a longer life span while being of high operating efficiency. Motor control methods have been developed and both of these methods have been implemented in this work to analyze the performance of a Brushless DC (BLDC) motor. This purpose of this work was to evaluate how the speed (RPM) of the BLDC motor changes as the voltage levels vary (from 1V to 24V). The Proposed method eliminates the Hall Sensor and using the back-EMF signals for rotor estimation, thereby reducing system complexity and cost. The Hall sensor informs the controller of the motor's position in the sensor based approach while in the sensorless method, the motorʹs position is estimated with the back-EMF theory. This contributes to lowering costs. The RPM range for motors without sensor RPM is from 120 RPM to 2880 RPM and for motors with sensors from 99 RPM to 2180 RPM. This allows the BLDC motors to enhance the effective control system reliability at low cost. It has many useful applications in electric vehicles, automated tools usage and robotics.
This paper presents an efficient method for calculating AC copper loss in interior permanent magnet synchronous motor (IPMSM) with rectangular conductors, considering pulse width modulation (PWM) current harmonics. Th...
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ISBN:
(数字)9798350348958
ISBN:
(纸本)9798350348965
This paper presents an efficient method for calculating AC copper loss in interior permanent magnet synchronous motor (IPMSM) with rectangular conductors, considering pulse width modulation (PWM) current harmonics. The inverter-fed current for driving IPMSM can be decomposed into fundamental and harmonic currents. The proposed method first utilizes magneto-static finite element analysis (MS FEA) to compute the magnetic vector potential (MVP) generated by the fundamental current. Next, the frozen permeability method linearizes the FEA model by keeping the permeability of iron core. A single harmonic current is input into linear-MS FEA to compute MVP without permanent magnet excitation. The MVP of other harmonic currents are derived using linear fitting. The linear fitting of MVP is validated with FEA. Finally, the AC copper loss is then calculated by summing the contributions from the MVP of each current component.
This article presents a reduction method of circulating current in parallel three-level inverters using modified discontinuous pulse-widthmodulation (DPWM) based on an interleaving scheme. The harmonics and current r...
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This article presents a reduction method of circulating current in parallel three-level inverters using modified discontinuous pulse-widthmodulation (DPWM) based on an interleaving scheme. The harmonics and current ripple are the same as that of a single inverter with the same current capacity as the parallel system with DPWM. An interleaved DPWM improves the output current quality. However, a circulating current is generated by the asynchronous phase carriers. The circulating current limits the power rating. To alleviate these problems, the proposed method reduces the high-frequency circulating current with switching frequency by 79% even at a high modulation index. The switching sequence and high-frequency circulating current are analyzed to prove the performance of the proposed method. The effectiveness and reliability of the proposed reduction method are compared to the conventional SVM. The validity of the proposed method is verified through simulations and experimental results.
The authors propose a current fluctuation reduction strategy based on optimal three-space-vector pulse-widthmodulation (TSVPWM), which is used to improve the service-life of the dc-link electrolytic capacitors in two...
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The authors propose a current fluctuation reduction strategy based on optimal three-space-vector pulse-widthmodulation (TSVPWM), which is used to improve the service-life of the dc-link electrolytic capacitors in two-level three-phase voltage-source inverter (VSI) system. Differing from the typical SVPWM-based method that employs two adjacent active voltage vectors and zero voltage vectors to synthesise the reference voltage, the proposed strategy selects the required voltage vectors based on the minimum dc-link electrolytic capacitor current fluctuation. With the proposed strategy, an objective function for the root-mean-square value of dc-link electrolytic capacitor current is first constructed under the constraint of eight permissible voltage vectors. And then, by solving the minimum of the objective function through the piecewise linear programming, the optimal three voltage vectors under the different modulation ratios and load power factors are obtained accordingly, so as to achieve the minimum dc-link electrolytic capacitor current fluctuations during each switching period. Meanwhile, a PWM implementation scheme based on positive-negative double carrier signals is presented, which not only simplifies the implementation process but also effectively reduces the switching losses of power devices. Finally, the experimental results demonstrate that the proposed strategy can minimise the dc-link electrolytic capacitor current fluctuation under different working conditions. Based on space voltage vector, a voltage vector combination was derived to minimise the capacitor current within a single switching cycle. Compared to the traditional SVPWM, experimental results have shown that the rms value of capacitor current can be reduced by up to 37%.image
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