In this paper, fast and compact implementations for code-based signature are presented. Existing designs are either using enormous memory storage or suffering from slow issuing speed of signatures. A vastly optimized ...
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In this paper, fast and compact implementations for code-based signature are presented. Existing designs are either using enormous memory storage or suffering from slow issuing speed of signatures. A vastly optimized new design solving these problems is proposed by exploiting quasi-cyclic low-density generator matrix codes at different levels. In particular, this paper provides a new algorithmic enhancement of signature generation and gives detailed and optimized solutions for critical steps of this algorithm. The design presented in this paper is the fastest implementation of code-based signatures in open literature. It is shown, for instance, that our implementation of signature generation engine can generate approximately 60 000 signatures per second on a Xilinx Virtex-6 FPGA, requiring only 5992 slices and 60 memory blocks. In addition, a very compact implementation is also provided, producing 5438 signatures per second with only 18 memory blocks.
In this paper, we present a compact design for the code based signature called LEDAsig with side channel resistance. Existing implementations concentrate on the high-speed feature while few of them have considerations...
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In this paper, we present a compact design for the code based signature called LEDAsig with side channel resistance. Existing implementations concentrate on the high-speed feature while few of them have considerations on area or power efficiency which are particularly decisive for low-cost or power constrained IoT applications. We propose an area-efficient FPGA architecture for systematically rotating the qc-ldgm codes amongst the block RAMs with read-first mode. Additionally, the side channel vulnerability of LEDAsig is carefully examined, and protective masking schemes are introduced accordingly to safeguard our design from power analysis attacks. Effectiveness of these schemes is verified on SAKURA-G FPGA board. Up till now, the design presented in this work is the most compact one and also the first side-channel secure one addressing first-order and (univariate) second-order differential power analysis for the code based signature schemes in the open literature. We show for instance that our first-order (second-order) protected implementation can sign a signature in 117 (203) ms on a Xilinx Spartan-6 FPGA, occupying only 622 (1142) slices, and therefore is a prospective candidate for post-quantum signature schemes in low-resource settings.
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