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A qc-ldpc code Based Digital Signature Algorithm

JOURNAL OF INFORMATION SCIENCE AND ENGINEERING 2019年第5期35卷 1061-1074页

作者： Ren, Fang Yang, Xue-Fei Zheng, Dong Xian Univ Posts & Telecommun Sch Telecommun & Informat Engn Xian 710121 Shaanxi Peoples R China Xian Univ Posts & Telecommun Natl Engn Lab Wireless Secur Xian 710121 Shaanxi Peoples R China

Courtois-Finiasz-Sendrier (CFS) digital signature algorithm, which proposed in 2001, is the most important code based digital signature algorithm and can resist the known attack of quantum algorithms such as Shor algorithm and Grover algorithm. But the efficiency of CFS is very low because of the extremely low signing speed and the large public key size. In this paper, a variation of CFS algorithm is presented. Instead of the Goppa code and the Patterson decoding algorithm, the new algorithm selects the Quasi-Cyclic Low Density Parity Check (qc-ldpc) code and the Belief Propagation (BP) decoding algorithm in the signing process. Compared with CFS algorithm, the new algorithm greatly reduces the storage space of public key and improves the efficiency of signature without compromising the security.

关键词： code based cryptography digital signature qc-ldpc code decoding algorithm CFS algorithm

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Optimization of Bilayer Lengthened qc-ldpc code for Relay channel Based on Differential Evolution

Optimization of Bilayer Lengthened QC-LDPC code for Relay ch...

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7th International Conference on Wireless Communications, Networking and Mobile Computing (WiCOM)

作者： Xu, Hua Yancheng Teachers Univ Sch Phys & Elect Engn Yancheng Peoples R China

ISBN: (纸本)9781424462520

A novel optimization algorithm to design a bilayer lengthened qc-ldpc code for relay channel is proposed in this paper, which combine differential evolution algorithm and bilayer graph for ldpc codes. We aim to construct qc-ldpc codes with best girth(maximum girth and minimum numbers of shortest cycles) both at relay node and destination node. Proposed algorithm is composed of two steps, first the exponent matrix of qc-ldpc code for lower graph is searched by differential evolution algorithm, then the exponent matrix of qc-ldpc code for overall graph is also found by differential evolution algorithm based on the obtained exponent matrix for lower graph. Simulation results verify the validity of proposed algorithm. Constructed qc-ldpc codes may perform well both at relay node and destination node.

关键词： qc-ldpc code girth differential evolution

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FPGA implementation of highly secure, hardware-efficient qc-ldpc code-based nonlinear cryptosystem for wireless sensor networks

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INTERNATIONAL JOURNAL OF COMMUNICATION SYSTEMS 2017年第10期30卷 1-16页

作者： Stuart, Celine Mary Deepthi, P. P. Natl Inst Technol Dept Elect & Commun Engn Calicut Kerala India

This paper presents the design and implementation of an integrated architecture for embedding security into quasi-cyclic (qc) low-density parity-check (ldpc) code-based cryptographic system through a nonlinear function of low hardware complexity. Instead of using standard S-boxes for implementation of nonlinear function, this paper considers a method on the basis of maximum length cellular automata (CA), so that enhanced security can be achieved with simple hardware structure. The proposed system adopts a lightweight random bit stream generator on the basis of linear feedback shift register (LFSR) for generating random error vectors, so that a large number of vectors with very good cryptographic properties can be made available with low hardware cost. Different permutation patterns generated for different message blocks help to provide good degrees of freedom for tuning security with reasonable key size. The hardware architecture for the proposed system is developed and validated through implementation on Xilinx Spartan 3S500E. Analytical and synthesis results show that the proposed scheme is lightweight and offers very high security through continuously changing parameters, thus making it highly suitable for resource-constrained applications.

关键词： cellular automata cryptosystem ECBC LFSR qc-ldpc code

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A 3.0 Gb/s Throughput Hardware-Efficient Decoder for Cyclically-Coupled qc-ldpc codes

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2016年第1期63卷 134-145页

作者： Lu, Qing Fan, Jianfeng Sham, Chiu-Wing Tam, Wai M. Lau, Francis C. M. Hong Kong Polytech Univ Elect & Informat Engn Dept Hong Kong Hong Kong Peoples R China

In this paper, we propose a new class of quasi-cyclic low-density parity-check (qc-ldpc) codes, namely cyclically-coupled qc-ldpc (CC-qc-ldpc) codes, and their RAM-based decoder architecture. CC-qc-ldpc codes have a simple structure and are constructed by cyclically-coupling a number of qc-ldpc subcodes. They can achieve throughput and error performance as excellent as ldpc convolutional codes, but with much lower hardware requirements. They are therefore promising candidates for future generations of communication systems such as long-haul optical communication systems. In particular, a rate-5/6 CC-qc-ldpc decoder has been implemented onto a field-programmable gate array (FPGA) and it achieves a throughput of 3.0 Gb/s at 100 MHz clock rate with 10-iteration decoding. No error floor is observed up to an E-b/N-0 of 3.50 dB, where all 1.14 x 10(16) transmitted bits have been decoded correctly.

关键词： Cyclically-coupled qc-ldpc code decoder architecture FPGA implementation qc-ldpc code

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Nonlinear Cryptosystem Based on qc-ldpc codes for Enhanced Security and Reliability with Low Hardware Complexity and Reduced Key Size

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WIRELESS PERSONAL COMMUNICATIONS 2017年第3期96卷 4177-4197页

作者： Stuart, Celine Mary Deepthi, P. P. Natl Inst Technol Calicut Dept Elect & Commun Engn Calicut 673601 Kerala India

The main issues to be addressed in resource limited devices are security, reliability and hardware complexity. Cryptosystems that combine encryption and error correction in a single step can offer a good solution to meet these issues. In this work, a nonlinear cryptosystem based on structured Low-Density Parity-Check code that offers small key size, low hardware complexity and high security against differential type of attack is proposed. The method adopted to introduce nonlinearity in a cryptosystem plays a key role in deciding the hardware complexity and security of the overall system. The work adopts a method for generating nonlinear function using maximum length Cellular Automata, so that enhanced security can be attained without going for a complex hardware structure. Also a light weight stream cipher is adopted for generating random error vectors for encryption and addition of intentional noise in such a way that the security is increased by a large margin at a low hardware cost. Different permutation matrices are generated for different message blocks for achieving good degrees of freedom with reasonable key size. Analysis shows that the proposed system provides high security with smaller key size and lower hardware complexity when compared with a nonlinear cryptosystem called Error Correction Based Cipher.

关键词： Cryptosystem qc-ldpc code Block chaining ECBC Differential cryptanalysis

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A joint encryption-encoding scheme using qc-ldpc codes based on finite geometry

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SCIENTIA IRANICA 2024年第17期31卷 1504-1516页

作者： Khayami, Hossein Eghlidos, Taraneh Aref, Mohammad Reza Sharif Univ Technol Dept Elect Engn Informat Syst & Secur Lab Tehran Iran Sharif Univ Technol Elect Res Inst Tehran 11365 Iran

Joint encryption-encoding schemes have been released to fulfill both reliability and security desires in a single step. Using Low Density Parity-Check (ldpc) codes in joint encryption-encoding schemes, as an alternative to classical linear codes, would. shorten the key size as well as improving error correction capability. In this article, a joint encryption-encoding scheme using Quasi-Cyclic Low Density Parity-Check (qc-ldpc) codes based on finite geometry is presented. It is observed that our proposed scheme not only outperforms its predecessors in key size and transmission rate, but also remains secure against all known cryptanalyses of code-based secret key cryptosystems. In this paper, we have proposed an idea to make qc-ldpc based cryptosystems secure against reaction attacks. It is subsequently shown that our scheme benefits from low computational complexity. By taking the advantage of qc-ldpc codes based on finite geometry, the key size of our scheme is very close to its target security level. In addition, using the proposed scheme, a wide range of desirable transmission rates are achievable. This variety of codes makes our cryptosystem suitable for a number of different communication and cryptographic standards such as Wireless Personal Area Networks (WPAN) and Digital Video Broadcasting (DVB). (c) 2024 Sharif University of Technology. All rights reserved.

关键词： Joint encryption-encoding Secure channel coding qc-ldpc code code-based cryptography Finite geometry

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Energy-efficient ldpc codec design using cost-effective early termination scheme

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IET COMPUTERS AND DIGITAL TECHNIQUES 2019年第2期13卷 118-125页

作者： Lin, Cheng-Hung Wu, Yuan-Syun Song, Chen-Pei Yuan Ze Univ Dept Elect Engn Jhongli 32003 Taiwan

Here, the authors propose an energy-efficient codec design using a rate-0.91 systematic quasi-cyclic-low-density parity-check (qc-ldpc) code. A cost-effective early termination (ET) scheme is presented for efficiently terminating the decoding iterations and maintaining desirable correcting performance. Compared with no ET scheme, the cost-effective ET scheme achieves 54.6% energy reduction with 1.7% area overhead. Finally, the proposed qc-ldpc codec employing the cost-effective ET scheme is implemented in a prototyping chip of 9.86 mm(2) core area using the TSMC 90 nm CMOS technology. Compared with the other decoder chips, the prototyping codec operating at 278 MHz achieves the best decoding energy efficiency of 156 pJ/bit with a high decoding throughput of 4.3 Gbps. The prototyping codec also achieves a high encoding throughput of 4.4 Gbps.

关键词： codecs decoding parity check codes CMOS integrated circuits cyclic codes iterative decoding energy-efficient ldpc codec design cost-effective early termination scheme energy-efficient codec design decoding iterations ET scheme qc-ldpc codec decoding energy efficiency energy reduction quasicyclic-low-density parity-check code TSMC CMOS technology qc-ldpc code size 90 0 nm frequency 278 0 MHz size 9 86 mm bit rate 4 3 Gbit s bit rate 4 4 Gbit s

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On Construction of Low-Density Parity-Check codes for Ultra-Reliable and Low Latency Communications

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IEEE TRANSACTIONS ON COMMUNICATIONS 2024年第9期72卷 5290-5301页

作者： Zou, Linqi Yan, Hao Dong, Jie Li, Yong Chen, Pingping Lau, Francis C. M. Chongqing Univ Coll Comp Sci Chongqing 400044 Peoples R China Imperial Coll London Dept Elect & Elect Engn London SW7 2AZ England Singapore Univ Technol & Design Dept Sci Math & Technol Singapore 487372 Singapore Fuzhou Univ Dept Elect Informat Fuzhou 350108 Peoples R China Hong Kong Polytech Univ Dept Elect & Informat Engn Hong Kong 100872 Peoples R China

Low-density parity-check (ldpc) codes with protograph-based raptor-like (PBRL) structure have been chosen as the data channel coding scheme for the fifth-generation (5G) enhanced mobile broad band (eMBB) services. However, these 5G ldpc codes are not optimized for the scenarios of Ultra Reliable and Low Latency Communications (URLLC) and massive Machine Type Communications (mMTC) in which small transport block sizes are usually used. In this paper, a new method is proposed to construct PBRL ldpc codes for URLLC and mMTC. This method incorporates degree-distribution optimization, base matrix derived from parity-check matrix of quadratic residue codes, masking technique and modified progressive-edge-growth (PEG) algorithm. Simulation results show that the proposed PBRL ldpc codes outperform 5G ldpc short codes in terms of error-correcting performance.

关键词： codes Parity check codes 5G mobile communication Ultra reliable low latency communication QR codes Standards Finite element analysis PBRL ldpc code qc-ldpc code quadratic residue code

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Lightweight Key Encapsulation Using ldpc codes on FPGAs

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IEEE TRANSACTIONS ON COMPUTERS 2020年第3期69卷 327-341页

作者： Hu, Jingwei Baldi, Marco Santini, Paolo Zeng, Neng Ling, San Wang, Huaxiong Nanyang Technol Univ Div Math Sci Singapore 639798 Singapore Marche Polytech Univ Dept Informat Engn I-60121 Ancona Italy

In this paper, we present a lightweight hardware design for a recently proposed quantum-safe key encapsulation mechanism based on qc-ldpc codes called LEDAkem, which has been admitted as a round-2 candidate to the NIST post-quantum standardization project. Existing implementations focus on high speed while few of them take into account area or power efficiency, which are particularly decisive for low-cost or power constrained IoT applications. The solution we propose aims at maximizing the metric of area efficiency by rotating the qc-ldpc code representations amongst the block RAMs in digit level. Moreover, optimized parallelized computing techniques, lazy accumulation and block partition are exploited to improve key decapsulation in terms of area and timing efficiency. We show for instance that our area-optimized implementation for 128-bit security requires 6.82 x 10(5) cycles and 2.26 x 10(6) cycles to encapsulate and decapsulate a shared secret, respectively. The area-optimized design uses only 39 slices (3 percent of the available logic) and 809 slices (39 percent of the available logic) for key encapsulation and key decapsulation respectively, on a small-size low-end Xilinx Spartan-6 FPGA.

关键词： Post-quantum cryptography key encapsulation mechanism qc-ldpc code FPGA implementation

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Design and implementation of hardware-efficient modified Rao-Nam scheme with high security for wireless sensor networks

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JOURNAL OF INFORMATION SECURITY AND APPLICATIONS 2016年 29卷 65-79页

作者： Stuart, Celine Mary Spandana, K. Dhanaraj, K. J. Pattathil, Deepthi P. Natl Inst Technol Calicut Dept Elect & Commun Engn Calicut 673601 Kerala India

This paper presents the design and implementation of a crypto channel coder with very low hardware complexity and high security for securing communication in resource-constrained applications such as Wireless Sensor Networks (WSNs). The integrated secure channel coder system is proposed as a modification of the Rao-Nam (RN) scheme by embedding security in a structured Low-Density Parity-Check (ldpc) code. A novel stream ciphering method based on the Linear Feedback Shift Register (LFSR) with high throughput is incorporated to generate random error vectors, so that a large number of vectors with very good cryptographic properties can be made available with simple hardware. An efficient design method to vary the encryption matrix and the intentional error vector with each message block provides high degrees of freedom for an intended receiver without compromising hardware simplicity. Prototypes of the proposed encoder architecture with both (28, 14) and (248, 124) Quasi-Cyclic (qc) ldpc codes have been implemented on Xilinx Field Programmable Gate Array (FPGA) Spartan 3E kit using Very High Speed Integrated Circuit Description Language (VHDL). Analytical and synthesis results show that this scheme is highly suitable for resource-constrained applications such as wireless sensor networks due to its low hardware complexity and high security. (C) 2016 Elsevier Ltd. All rights reserved.

关键词： qc-ldpc code LFSR Cryptosystem RN scheme

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