This paper proposes a decoder architecture for low-density parity-check convolutionalcode (ldpcCC). Specifically, the ldpcCC is derived from a quasi-cyclic (qc) ldpc block code. By making use of the quasi-cyclic stru...
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This paper proposes a decoder architecture for low-density parity-check convolutionalcode (ldpcCC). Specifically, the ldpcCC is derived from a quasi-cyclic (qc) ldpc block code. By making use of the quasi-cyclic structure, the proposed ldpcCC decoder adopts a dynamic message storage in the memory and uses a simple address controller. The decoder efficiently combines the memories in the pipelining processors into a large memory block so as to take advantage of the data-width of the embedded memory in a modern field-programmable gate array (FPGA). A rate-5/6 qc-ldpcCC has been implemented on an Altera Stratix FPGA. It achieves up to 2.0 Gb/s throughput with a clock frequency of 100 MHz. Moreover, the decoder displays an excellent error performance of lower than 10(-13) at a bit-energy-to-noise power-spectral-density ratio(E-b/N-0) of 3.55 dB.
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