This paper proposes a cyclic shift decomposition (CSD) algorithm to perform multi-way cyclic shifts with low complexity in the quasi-cycliclow-densityparity-check (QC-LDPC) decoder. The proposed algorithm decomposes...
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This paper proposes a cyclic shift decomposition (CSD) algorithm to perform multi-way cyclic shifts with low complexity in the quasi-cycliclow-densityparity-check (QC-LDPC) decoder. The proposed algorithm decomposes the cyclic shift into a common cyclic shift and a private cyclic shift. Based on the proposed CSD algorithm, a low-complexity multi-way and reconfigurable cyclic shift network (CSN) for QC-LDPC codes is proposed. The proposed CSN is composed of the shared component, which performs the common cyclic shift, and the repeated component, which performs the private cyclic shift. Each component can support reconfigurability for given QC-LDPC codes. By introducing the single-path shared component, only the complexity of the multi-path repeated component increases linearly as the number of multi-way paths increases. A complexity analysis of each component is also proposed. Based on the complexity analysis, the proposed CSN can perform multi-way and reconfigurable cyclic shifts with low complexity in the QC-LDPC decoder. The implementation results show that the areas of the proposed four-way CSN are 0.227 mm(2) and 0.276 mm(2) for the IEEE 802.11n/ac and IEEE 802.16e QC-LDPC codes, respectively, with 130 nm CMOS technology. The area saving per each-way is from 13.8% to 86.5% compared with previously presented works(1).
Layered decoding (LD) facilitates a partially parallel architecture for performing belief propagation (BP) algorithm for decoding low-densityparity-check (LDPC) codes. Such a schedule for LDPC codes has, in general, ...
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Layered decoding (LD) facilitates a partially parallel architecture for performing belief propagation (BP) algorithm for decoding low-densityparity-check (LDPC) codes. Such a schedule for LDPC codes has, in general, reduced implementation complexity compared to a fully parallel architecture and higher convergence rate compared to both serial and parallel architectures, regardless of the codeword length or code-rate. In this paper, we introduce a modified shuffling method which shuffles the rows of the parity- check matrix (PCM) of a quasi- cyclic LDPC (QC-LDPC) code, yielding a PCM in which each layer can be produced by the circulation of its above layer one symbol to the right. The proposed shuffling scheme additionally guarantees the columns of a layer of the shuffled PCM to be either zero weight or single weight. This condition has a key role in further decreasing LD complexity. We show that due to these two properties, the number of occupied look-up tables (LUTs) on a field programmable gate array (FPGA) reduces by about 93% and consumed on- chip power by nearly 80%, while the bit error rate (BER) performance is maintained. The only drawback of the shuffling is the degradation of decoding throughput, which is negligible for low values of E-b/N-0 until the BER of 1e-6.
In this paper, the design of the LDPC decoder architecture in IEEE 802.11n/ac is proposed. The proposed decoder is used to the partial parallel architecture to provide 2 Gbps throughput at 200 MHz clock frequency. In ...
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ISBN:
(纸本)9781479954797
In this paper, the design of the LDPC decoder architecture in IEEE 802.11n/ac is proposed. The proposed decoder is used to the partial parallel architecture to provide 2 Gbps throughput at 200 MHz clock frequency. In IEEE 802.11n/ac, 12 paritycheck metrics is provide to support diverse code rates and block lengths. Therefore the network between nodes is configured to be satisfied paritycheck metrics. However, the structure of the network increases the complexity of LDPC decoder. Hence, the optimized network generator is also proposed to reduce the complexity of the network.
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