The simplicity of regular mesh topology Network on Chip (NoC) architecture leads to reductions in design time and manufacturing cost. A weakness of the regular shaped architecture is its inability to efficiently suppo...
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The simplicity of regular mesh topology Network on Chip (NoC) architecture leads to reductions in design time and manufacturing cost. A weakness of the regular shaped architecture is its inability to efficiently support cores of different sizes. A proposed way in literature to deal with this is to utilize the region concept, which helps to accommodate cores larger than the the size in mesh topology NoC architectures. Region concept offers many new opportunities for NoC design, as well as provides new design issues and challenges. One of the most important among these is the design of an efficient deadlock free routing algorithm. Available adaptive routing algorithms developed for regular mesh topology cannot ensure freedom from deadlocks. In this paper, we list and discuss many new design issues which need to be handled for designing NoC systems incorporating cores larger than the the size. We also present and compare two deadlock free routing algorithms for mesh topology NoC with regions. The idea of the first algorithm is borrowed from the area of fault tolerant networks, where a network topology is rendered irregular due to faults in routers or links, and is adapted for the new context. We compare this with an algorithm designed using a methodology for design of application specific routing algorithms for communication networks. The application specific routing algorithm tries to maximize adaptivity by using static and dynamic communication requirements of the application. Our study shows that the application specific routing algorithm not only provides much higher adaptivity, but also superior performance as compared to the other algorithm in all traffic cases. But this higher performance for the second algorithm comes at a higher area cost for implementing network routers. (C) 2007 Elsevier B.V. All rights reserved.
Most standard cluster interconnect technologies are flexible with respect to network topology. This has spawned a substantial amount of research on topology-agnostic routing algorithms, which make no assumption about ...
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Most standard cluster interconnect technologies are flexible with respect to network topology. This has spawned a substantial amount of research on topology-agnostic routing algorithms, which make no assumption about the network structure, thus providing the flexibility needed to route on irregular networks. Actually, such an irregularity should be often interpreted as minor modifications of some regular interconnection pattern, such as those induced by faults. In fact, topology-agnostic routing algorithms are also becoming increasingly useful for networks on chip (NoCs), where faults may make the preferred 2D mesh topology irregular. Existing topology-agnostic routing algorithms were developed for varying purposes, giving them different and not always comparable properties. Details are scattered among many papers, each with distinct conditions, making comparison difficult. This paper presents a comprehensive overview of the known topology-agnostic routing algorithms. We classify these algorithms by their most important properties, and evaluate them consistently. This provides significant insight into the algorithms and their appropriateness for different on- and off-chip environments.
The interactions between adaptive routing algorithms incorporating learning automata and a variable window flow control algorithm are examined. The routing algorithms examined use two new discretised learning automata...
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The interactions between adaptive routing algorithms incorporating learning automata and a variable window flow control algorithm are examined. The routing algorithms examined use two new discretised learning automata to choose the minimum delay routes in the network. The first routing algorithm can choose between two possible candidate paths. The second algorithm, using a new fast and accurate multi-action discretised automaton can choose between as many candidate paths as desired. The flow control algorithm is a threshold-based variable window algorithm that decreases the window size when a predefined delay threshold is exceeded and increases it below this threshold. The interactions between the two algorithms are studied. The resulting scheme is compared with similar schemes reported in the literature via simulations. Simulation results are presented which show that the new scheme performs quite well in both normal and abnormal network conditions.
In order to optimize traffic flows and power consumption of network components, various green routing algorithms and protocols have been proposed. These algorithms and protocols apply different techniques to attain th...
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In order to optimize traffic flows and power consumption of network components, various green routing algorithms and protocols have been proposed. These algorithms and protocols apply different techniques to attain their own goals. One of the most important techniques is the sleep-scheduling technique that switches the status of the network components, nodes or links, into active/inactive modes. There are four characteristics affecting the power and performance of communication networks which distinguish green routing algorithms and protocols, namely the sleep-scheduled component, decision structure, network traffic awareness, and quality of service awareness. In this paper, a method is proposed to model, evaluate, and compare the power and performance of the green routing algorithms that use the sleep-scheduling technique. We apply stochastic activity networks to model and analyze the routing algorithms with respect to the network topology. The results obtained from the comparison of the algorithms, validated with the OMNeT++ simulator, can be used by network administrators to make the right decisions.
In this paper, we investigate the problem of routing connections in ail-optical networks while allowing for degradation of routed signals by different optical components. To overcome the complexity of the problem, we ...
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A new class of wireless sensor networks that harvest power from the environment is emerging because of its intrinsic capability of providing unbounded lifetime. While a lot of research has been focused on energy-aware...
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A new class of wireless sensor networks that harvest power from the environment is emerging because of its intrinsic capability of providing unbounded lifetime. While a lot of research has been focused on energy-aware routing schemes tailored to battery-operated networks, the problem of optimal routing for energy harvesting wireless sensor networks (EH-WSNs) has never been explored. The objective of routing optimization in this context is not extending network lifetime, but maximizing the workload that can be autonomously sustained by the network. In this work we present a methodology for assessing the energy efficiency of routing algorithms for networks whose nodes drain power from the environment. We first introduce the energetic sustainability problem, then we define the maximum energetically sustainable workload (MESW) as the objective function to be used to drive the optimization of routing algorithms for EH-WSNs. We propose a methodology that makes use of graph algorithms and network simulations for evaluating the MESW starting from a network topology, a routing algorithm and a distribution of the environmental power available at each node. We present a tool flow implementing the proposed methodology and we show comparative results achieved on several routing algorithms. Experimental results highlight that routing strategies that do not take into account environmental power do not provide optimal results in terms of workload sustainability. Using optimal routing algorithms may lead to sizeable enhancements of the maximum sustainable workload. Moreover, optimality strongly depends on environmental power configurations. Since environmental power sources change over time, our results prompt for a new class of routing algorithms for EH-WSNs that are able to dynamically adapt to time-varying environmental conditions. (C) 2007 Elsevier B.V. All rights reserved.
I propose an integrated hybrid optical node ( i-HON) architecture that is designed to combine both packet-switched and circuit-switched data in an effective manner to maximize link utilization, minimize communication ...
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I propose an integrated hybrid optical node ( i-HON) architecture that is designed to combine both packet-switched and circuit-switched data in an effective manner to maximize link utilization, minimize communication latencies, and improve overall performance. I demonstrate the feasibility of i-HON by proposing a single wavelength optical header encoder and self-routing binary-encoded optical header address processing. I then develop dynamic hybrid routing heuristics and adapt these to the novel dynamic reconfiguration and routing algorithms suited for asynchronous bufferless optical networks that incorporate optical routing logic. I compare the performance of the presented algorithms. I use simulation results to show that i-HON provides overall system throughput performance improvements of up to 40% with similar to 50% reduction in network latency. (c) 2007 Optical Society of America.
An optimal [1.5N(1/2)] lower bound is shown for oblivious routing on the mesh of buses: a two-dimensional parallel model consisting of N-1/2 x N-1/2 processors and N-1/2 TOW and N-1/2 column buses but no local connect...
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An optimal [1.5N(1/2)] lower bound is shown for oblivious routing on the mesh of buses: a two-dimensional parallel model consisting of N-1/2 x N-1/2 processors and N-1/2 TOW and N-1/2 column buses but no local connections between neighboring processors. Many lon er bound proofs for routing on mesh-structured models use a single instance (adversary) which includes difficult packet-movement. This approach does not work in our case, our proof is one of the rare cases which really exploit the fact that the routing algorithm has to cope with many different instances. Note that the two-dimensional mesh of buses includes 2N(1/2) buses and each processor can access two different buses. Apparently the three-dimensional model provides more communication facilities, namely including 3N(2/3) buses, and each processor can access three different buses. Surprisingly, however, the oblivious routing on the three-dimensional mesh of buses needs more time, i.e., Omega(N-2/3) steps, which is another important result of this paper. (C) 2000 Academic Press.
The three-dimensional Network-on-Chip (3D NoC) has been proposed to solve the complex on-chip communication issues in multicore systems by using die stacking technology in recent years. However, the high integration d...
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The three-dimensional Network-on-Chip (3D NoC) has been proposed to solve the complex on-chip communication issues in multicore systems by using die stacking technology in recent years. However, the high integration density of the stacking dies at high operating frequency results in large power density. Furthermore, the unequal thermal conductance of different logic layers leads the 3D NoC to face a much severer thermal problem than 2D NoC. Those thermal issues may limit the performance gain of 3D integration and cause lower reliability of the 3D NoC designs. To ensure the thermal safety, the 3D NoC systems generally require a better cooling method, which can be classified into "technological approaches" and "algorithmic/architectural approaches." The technological approaches work efficiently for removal of internal thermal hotspots through extra devices but results in drastically increasing fabrication cost. On the other hand, the algorithmic/architectural design approaches aim to use the approaches of intelligent packet data delivery and temperature control to maximize performance under thermal constraints. Compared with technological approaches, they can control the system temperature at much lower extra circuit/device cost. In this article, we focus on the algorithmic/architectural design approaches and review the modern packet routing algorithms and thermal managements for thermal-aware 3D NoC systems. Firstly, we introduce the thermal challenges of 3D NoC system and review the encountered design challenges. Then, recent developed techniques to handle the thermal challenges of 3D NoC systems are addressed.
3-Dimensional Networks-on-Chip (3D NoC) have emerged as the promising solution for scalability, power consumption and performance demands of next generation Systems-on-Chip (SoCs) interconnect. Due to the cost in term...
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3-Dimensional Networks-on-Chip (3D NoC) have emerged as the promising solution for scalability, power consumption and performance demands of next generation Systems-on-Chip (SoCs) interconnect. Due to the cost in terms of thermal, yield, chip area and design complexity, minimizing the number of Through-Silicon-Via (TSVs) in 3D ICs has become on the most important design issues. In this paper, we will present several stable, simple and deadlock-free generic routing algorithms for 3D NoCs with different reduced vertical link density topologies, which can maintain the 3D NoCs performance and save the system cost (TSV number, chip area, system power, etc.). The experimental results have been extracted from our cycle-accurate GSNOC simulator and have shown that our routing algorithms can maintain the system performance up to reducing 50% of TSVs number in comparison to the 100% TSVs number with ZXY routing algorithm configuration. (C) 2013 Elsevier B.V. All rights reserved.
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