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A simple implement of submicron meter rram array based on porous SiO₂ film with uniform and large pores

VACUUM 2016年第0期132卷 119-122页

作者： Sun, X. Y. Pan, X. Q. Wu, C. G. Bai, X. Y. Luo, W. B. Shuai, Y. Zhong, Z. Q. Univ Elect Sci & Technol China State Key Lab Elect Thin Films & Integrated Devic Chengdu 610054 Peoples R China

Resistive Random Access Memory (rram) array is considered as a promising trend for future memory devices. At present, the integration of rram array into CMOS circuit is limited by the density and scale of the memory element. In this paper, a new way to fabricate rram array with submicron meter range element size is proposed. Porous SiO2 film with large and uniform through-holes is prepared as nano template for device fabrication. Plasma oxidation is utilized to grow 100 nm titanium oxide resistive switching (RS) layer. Discrete circular RS cells with diameter of 400 nm are obtained, with a vertical structure of Ag-TiO2-Ti-Pt-Ti-SL from top to bottom. Good and uniform RS properties are acquired by conductive Atomic Force Microscope (cAFM). (C) 2016 Elsevier Ltd. All rights reserved.

关键词： rram array Porous structure control Uniform RS property

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The Synthesis Method of Logic Circuits Based on the NMOS-Like rram Gates

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IEEE ACCESS 2021年 9卷 54466-54477页

作者： Cui, Xiaole Ma, Ye Wei, Feng Cui, Xiaoxin Peking Univ Key Lab Integrated Microsyst Shenzhen Grad Sch Shenzhen 518055 Peoples R China Peking Univ Inst Microelect Beijing 100871 Peoples R China

The synthesis method of logic circuits based on the rram (Resistive Random Access Memory) devices is of great concern in recent years. Inspired by the CMOS-like rram based logic gates, this work proposes a NMOS-like rram gate family. The advantages of the proposed NMOS-like rram gates include: (1) all the gate circuits are array-implementable;(2) the gate family is logic complete;(3) the NOR, AND and NOT gates only consume single cycle respectively in the computation phase;(4) the gate circuits save half number of rram devices compared with the CMOS-like rram based counterparts. Furthermore, the synthesis method of logic circuits based on the NMOS-like rram gates is proposed and discussed. The single-cycle NMOS-like rram gates are utilized in priority under the constraints of the logic block. The features of the proposed synthesis method are: (1) it generates the high-performance logic circuits because the NMOS-like rram based gates work in parallel;(2) the logic block based on the proposed NMOS-like gates can be realized in the rram array;(3) the large-scale logic functions can be implemented by cascading the logic blocks. The in-array full-adder circuit generated by the proposed synthesis method only consumes three cycles in minimum, which outperforms the previous rram based counterpart. The synthesis results on the benchmark circuits show that the proposed synthesis method is able to generate the high-performance circuit in rram arrays for arbitrary logic functions.

关键词： Logic gates Resistance Logic arrays Random access memory Logic functions Electrodes rram array NMOS-like rram gates computation in memory synthesis method

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Reliability-Aware Design Strategies for Stateful Logic-in-Memory Architectures

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IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY 2020年第2期20卷 278-285页

作者： Zanotti, Tommaso Puglisi, Francesco Maria Pavan, Paolo Univ Modena & Reggio Emilia Dipartimento Ingn Enzo Ferrari I-41125 Modena Italy

The in-memory computation of logic operations is a promising paradigm that could enable the development of highly efficient computing architectures, ideal for battery-powered devices. Indeed, Resistive Random Access Memory (rram) devices and the material implication logic (IMPLY) have been experimentally demonstrated to enable low-power logic-in-memory (LIM) circuits. Still, device and circuit non-idealities (e.g., the strong sensitivity to driving voltage variations) introduce several reliability challenges that must be addressed with appropriate device models. Often, general-purpose or simplified models are used in the analysis, thus resulting in questionable estimations and designs. In this work, we use a physics-based rram compact model, comprehensive of device non-idealities, to study the reliability of IMPLY-based LIM circuits. The analysis is first performed on the single IMPLY logic gate and then extended to an array implementation encompassing the effect of line parasitic resistances and node capacitances. We determine and quantitatively evaluate important metrics such as energy consumption and maximum array size, and derive appropriate design strategies aimed at improving the reliability of such circuits.

关键词： Materials reliability Compact model IMPLY logic-in-memory rram rram array

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Analysis of the statistics of device-to-device and cycle-to-cycle variability in TiN/Ti/Al:HfO2/TiN rrams

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MICROELECTRONIC ENGINEERING 2019年第0期214卷 104-109页

作者： Perez, E. Maldonado, D. Acal, C. Ruiz-Castro, J. E. Alonso, F. J. Aguilera, A. M. Jimenez-Molinos, F. Wenger, Ch. Roldan, J. B. IHP Leibniz Inst Innovat Mikroelekt Frankfurt Oder Germany Univ Granada Dept Elect & Tecnol Comp Granada Spain Univ Granada Dept Estadist & Invest Operat Granada Spain Brandenburg Med Sch Theodor Fontane Neuruppin Germany

In order to study the device-to-device and cycle-to-cycle variability of switching voltages in 4-kbit rram arrays, an alternative statistical approach has been adopted by using experimental data collected from a batch of 128 devices switched along 200 cycles. The statistical distributions of switching voltages have been usually studied by using the Weibull distribution. However, this distribution does not work accurately on Al:HfO2-based rram devices. Therefore, an alternative approach based on phase-type distributions is proposed to model the forming, reset and set voltage distributions. Experimental results show that in general the phase-type analysis works better than the Weibull one.

关键词： rram array Variability Weibull distribution Phase-type distribution

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Intelligent Computing with rram 11

Intelligent Computing with RRAM

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IEEE 11th International Memory Workshop (IMW)

作者： Yao, Peng Zhang, Wenqiang Zhao, Meiran Lin, Yudeng Wu, Wei Gao, Bin Qian, He Wu, Huaqiang Tsinghua Univ Inst Microelect Beijing Peoples R China

ISBN: (纸本)9781728109817

rram-based in-memory-computing is a promising approach to go beyond von Neumann architecture and attributes to remarkable improvement in power efficiency and performance density. In this work, we examine our developments in device optimization for high-linearity SET/RESET updating and analyze the device reliability issues. We further exhibit the experimental demonstrations for the perceptron and generative adversarial network ( GAN), showing how to combine algorithms and non-idea devices together. An end-to-end simulator was set up to evaluate the system performance ( the accuracy, latency and energy) with actual device performance. Lastly, we provide a guideline for array size optimization.

关键词： analog rram reliability in-memory-computing rram array system demonstration simulator

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Electrical characterization and modeling of 1T-1R rram arrays with amorphous and poly-crystalline HfO₂

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SOLID-STATE ELECTRONICS 2017年 128卷 187-193页

作者： Grossi, Alessandro Zambelli, Cristian Olivo, Piero Crespo-Yepes, Alberto Martin-Martinez, Javier Rodriguez, Rosana Nafria, Monserrat Perez, Eduardo Wenger, Christian Univ Ferrara Dip Ingn Via Saragat 1 I-44122 Ferrara Italy Univ Autonoma Barcelona Dept Elect Engn Bellaterra 08193 Spain IHP Technol Pk 25 D-15236 Frankfurt Oder Germany

In this work, a comparison between 1T-1R rram arrays, manufactured either with amorphous or polycrystalline Metal-Insulator-Metal cells, is reported in terms of performance, reliability, Set/Reset operations energy requirements, intra-cell and inter-cell variability during 10k endurance cycles and 100k read disturb cycles. The modeling of the 1T-1R rram array cells has been performed with two different approaches: (i) a physical model like the Quantum Point Contact (QPC) model was used to find the relationship between the reliability properties observed during the endurance and the read disturb tests with the conductive filament properties;(ii) a compact model to be exploited in circuit simulations tools which models the I-V characteristics of each memory cells technology. (C) 2016 Elsevier Ltd. All rights reserved.

关键词： rram array Forming Read window Energy saving

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Electrical characterization and modeling of pulse-based forming techniques in rram arrays

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SOLID-STATE ELECTRONICS 2016年第PartA期115卷 17-25页

作者： Grossi, Alessandro Zambelli, Cristian Olivo, Piero Miranda, Enrique Stikanov, Valeriy Walczyk, Christian Wenger, Christian Univ Ferrara Dipartimento Ingn I-44122 Ferrara Italy

The forming process, which corresponds to the activation of the switching filament in Resistive Random Access Memory (rram) arrays, has a strong impact on the cells' performances. In this paper we characterize and compare different pulse forming techniques in terms of forming time, yield and cell-to-cell variability on 4 kbits rram arrays. Moreover, post-forming modeling during Reset operation of correctly working and over formed cells has been performed. An incremental form and verify technique, based on a sequence of trapezoidal waveforms with increasing voltages followed by a verify operation that terminates when the expected switching behavior has been achieved, showed the best results. This procedure narrows the post-forming current distribution whereas reducing the Reset switching voltage and the operative current. These advantages materialize in a better control of the cell-to-cell variability and in an overall time and energy saving at the system level. (C) 2015 Elsevier Ltd. All rights reserved.

关键词： rram array Forming Read window Energy saving

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rram Refresh Circuit: A Proposed Solution To Resolve The Soft-Error Failures For HfO₂/Hf 1T1R rram Memory Cell 16

RRAM Refresh Circuit: A Proposed Solution To Resolve The Sof...

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26th ACM Great Lakes Symposium on VLSI (GLSVLSI)

作者： Tosson, Amr M. S. Anis, Mohab Wei, Lan Univ Waterloo Waterloo ON N2L 3G1 Canada Amer Univ Cairo New Cairo Cairo Governora Egypt

ISBN: (纸本)9781450342742

rram-based memory is a promising emerging technology for both on-chip and stand-alone non-volatile data storage in advanced technologies. In addition to its small dimensions, the rram device has many technological advantages including its low-programming voltages, high speed, low power, CMOS-compatible fabrication process, and potentially monolithic 3D integration. However, one of the critical challenges for rram technology is the reliability concerns due to retention and endurance failures. In this paper, we propose a novel Refresh circuit for 1T1R rram array which detects and distinguishes soft and hard errors from retention and endurance failures, as well as corrects the soft errors through refreshing. Using the HfO2/Hf rram array, our simulation results show that the proposed solution increases the resilience to soft-error of an 8Gb rram-based memory by 80% with a small penalty on the energy and delay of the Read operations (6% and 0.4% respectively). The proposed methodology can be used for other rram arrays with minor modifications to the design parameters depending on the characteristics of rram cell.

关键词： reliability rram array refresh

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