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BFT: a placement algorithm for non-rectangle task model in reconfigurable computing system

IET COMPUTERS AND DIGITAL TECHNIQUES 2016年第3期10卷 128-137页

作者： Wang, Chaohui Wu, Weiguo Nie, Shiqiang Qian, Depei Xi An Jiao Tong Univ Dept Comp Sci & Technol Xian Shaanxi Peoples R China Beihang Univ Sch Comp Sci & Engn Beijing 100191 Peoples R China

Task scheduling and placement problem is one of the most significant and time-consuming parts in reconfigurable computing (RC) system. Many investigators have explored on the subject, and most of the traditional studies are concentrated on the rectangle task model, which is inconsistent with objective task shape placed in a field programmable gate array (FPGA) but simplifies the system complexity. Rectangle task model produces inner fragments which reduces utilisation of reconfigurable resources in an FPGA. In this study, a task model transformation strategy and an innovative best-fit transformation (BFT) placement algorithm are proposed for a non-rectangle task model to improve the performance of an RC system in rejection rate and total execution time. According to simulation experiments, BFT algorithm reduced the rejection rate by 15% and 7% compared with that of the first-fit algorithm and the best-fit algorithm, respectively. Multi-shape placement algorithm and 3D compaction algorithm are also cited to compare with the BFT algorithm. The result shows that the BFT algorithm has less total execution time in short laxity period and lower rejection rate in large laxity period. Compared with 3D compaction algorithm, the proposed algorithm reduced the total execution time up to 10.79%.

关键词： reconfigurable architectures field programmable gate arrays processor scheduling BFT nonrectangle task model reconfigurable computing system task scheduling and placement problem RC system field programmable gate array FPGA system complexity reconfigurable resources task model transformation strategy innovative best-fit transformation placement algorithm total execution time rejection rate first-fit algorithm multishape placement algorithm 3D compaction algorithm

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reconfigurable computing system used in postgraduate innovative education

Reconfigurable computing system used in postgraduate innovat...

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2013 International Conference on Information and Communication Technology for Education (ICTE 2013)

作者： Zhiling Tang Lijuan Yu Simin Li Key Laboratory of Cognitive Radio and Information Processing (Guilin University of Electronic Technology) Ministry of Education

To resolve the problem of building a "bridge" between innovative thinking and innovative practice in postgraduate innovative education, we investigated the facilitation of postgraduate innovative education with the help of reconfigurable computing system. After analyzing the problem of postgraduate innovative education, then some cases of research assisted by reconfigurable computing system were introduced. So we believe reconfigurable computing system just is the suitable "bridge" we expected.

关键词： innovation education reconfigurable computing system

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Nominal decomposition of colour space transformation for the computer system for the reconfigurable computing and SA-C programming

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INTERNATIONAL JOURNAL OF COMPUTER APPLICATIONS IN TECHNOLOGY 2011年第2-3期42卷 204-212页

作者： Kuo, Jian-Long Natl Kaohsiung First Univ Sci & Technol Dept Mech & Automat Engn Kaohsiung 811 Taiwan

A nominal decomposition is proposed to compute the colour space transformation in single assignment C (AS-C) language to shorten the execution time. The chromaticity coordinate transformation will be used by using fixed-point nominal decomposition. The look-up table for the gamma curve function mapping is also developed by illustrating two Taylor expansion types. The variables are decomposed into two corresponding values: nominal value and base value. The numerical results will verify that the developed algorithm can save the execution time. The developed algorithm can be very useful to implement the computer display and printer system in the firmware interface aspects.

关键词： nominal decomposition RCS reconfigurable computing system SA-C single assignment C parallel computing VHDL colour space, chromaticity coordinate DFG data flow graph LUT look-up table

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High computing-Intensive Array system Design and Hardware Implement

High Computing-Intensive Array System Design and Hardware Im...

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IEEE 8th International Conference on ASIC

作者： Song, Yu-kun Wang, Xiao-lei Ni, Wei Zhang, Duo-li Du, Gao-ming Hefei Univ Technol Inst VLSI Design Hefei 230009 Peoples R China

ISBN: (纸本)9781424438686

This paper addresses a novel coarse grain dynamic reconfigurable computing system, called DReAC-2, design and hardware implement. A whole DReAC-2 system integrates a Nios II processor, which manages the whole reconfigurable system, and a dynamic reconfigurable coprocessor, which comprises of an 8x8 processing node array designed for high regularity, high computation-intensive tasks. Hardware prototype of DReAC-2 has been implemented on the ALTERA STRATIX II EP2S180 development board. According to task's nature, MIMD computing array can select either parallel-pipelined pattern or array-parallel pattern to gain the better performance. The experiment results show that DReAC-2 achieves much higher 10 similar to 100x factor than NIOS II processors, and 2x similar to 4x factors and higher precision than some others reconfigurable processors(1).

关键词： reconfigurable computing system High Computation-intensive Array-Parallel Parallel-Pipeline

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A gravity-directed temporal partitioning approach

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IEICE ELECTRONICS EXPRESS 2008年第10期5卷 366-373页

作者： Mehdipour, Farhad Noori, Hamid Honda, Hiroaki Inoue, Koji Murakami, Kazuaki Kyushu Univ Res Inst Informat Technol Fukuoka 812 Japan Inst Syst Informat Technol & Nanotechnol Fukuoka Japan Kyushu Univ Dept Informat Fukuoka 812 Japan

Reconfiguration latency has a significant impact on the system performance in reconfigurable systems. A temporal partitioning approach is introduced for partitioning data flow graphs for a reconfigurable system comprising a partial programmable fine-grained hardware. Residing eligibility inspired from the Universal gravitation law is introduced to depict the eligibility of a node to stay in succeeding configurations (partitions) and to prohibit it from being swapped in/out. Partitioning based on residing eligibility causes fewer nodes with different functionalities to be assigned to subsequent partitions. Thus, reconfiguration overhead time and also unused hardware space decreases due to common parts in consecutive configurations.

关键词： reconfigurable computing system temporal partitioning data flow graph

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Level sensitive cluster based partitioning algorithms for reconfigurable systems

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Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of Computer-Aided Design and Computer Graphics 2006年第5期18卷 667-673页

作者： Zhou, Bo Qiu, Weidong Chen, Yonghui Peng, Chenglian Department of Computer and Information Technology Fudan University Shanghai 200433 China

This paper presents a DAG (directed acyclic graph) partitioning algorithm for reconfigurable computing, called LSCBP (Level Sensitive cluster based Partitioning) algorithm, which partitions the whole task graph into small segments and keep task precedence relations under area constraints. The proposed heuristic function AS_Level can denote allocation priorities of the ready list and will be adjusted during the partitioning process. The heuristic function is constructed with the guideline of dependence first, earliest time first and fragment reuse. The proposed algorithm can overcome the drawback of CBP algorithm and its time complexity increases to O{|V|2+|E|}. For the same DAGs, the experimental results on random DAGs show that LSCBP algorithm can get less task-clusters (meaning less requirements for reconfigurable devices) and inter-cluster edges (meaning less communication costs) than CBP algorithm.

关键词： Directed acyclic graph FPGA Graph partitioning reconfigurable computing system Task cluster

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SHUM-uCOS: A RTOS using multi-task model to reduce migration cost between SW/HW tasks

SHUM-uCOS: A RTOS using multi-task model to reduce migration...

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9th International Conference on Computer Supported Cooperative Work in Design

作者： Zhou, B Qiu, WD Chen, Y Peng, CL Fudan Univ Dept Comp & Informat Technol Shanghai 200433 Peoples R China

ISBN: (纸本)1846000025

The design of embedded systems has become more complex than ever, and the design qualities depend more on the cooperation of multidisciplinary design teams: hardware engineers and software engineers in general. However, due to the lack of uniform programming model and system components for these different teams, the migrations costs of a function model from software to hardware are high. But these actions are necessary in the hardware-software partitioning of embedded systems, especially in the prototype designs. To cope with this problem, we adopt a uniform multi-task model and implement a RTOS (Real-Time Operating system), called SHUM-uCOS, which deals with hardware functions as same as software tasks. This RTOS uses uCOSII as its prototype, traces and manages the states of reconfigurable resources (FPGAs), which allows the execution of hardware tasks in a true multitasking manner. Moreover, SHUM-uCOS also defines a standard hardware-task interface, which supports share-bus protocol. It has been proved by experiments that SHUM-uCOS can shorten the migration time from software implementations to hardware implementations with the performance improvement.

关键词： reconfigurable computing system RTOS multi-task model uCOS

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Hardware object model and its application to the image processing

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 2004年第3期E87A卷 547-558页

作者： Kudo, K Myokan, Y Than, WC Akimoto, S Kanamaru, T Sekine, M Tokyo Univ Agr & Technol Dept Elect & Elect Engn Fac Technol Koganei Tokyo 1848588 Japan

To realize the hardware object which facilitates the application development in the reconfigurable computing system, a hardware module (HwModule) is proposed and implemented. To access the circuit in the HwModule from the standard PC without detailed knowledge of the hardware, an object manager (ObjectManager) is also implemented. With the help of the ObjectManager, the programmers can use the hardware objects like the usual software objects. The HwModule is applied to the image matching, and the easiness of the application development for the HwModule is confirmed.

关键词： reconfigurable computing system hardware object model wavelet transformation template matching

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