The paper promotes to construct a synthesizable VHDL model from a graphical representation of Petri Net. The VHDL code provides a clear semantics of graphically designed reconfigurable logic controller and serves as r...
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The paper promotes to construct a synthesizable VHDL model from a graphical representation of Petri Net. The VHDL code provides a clear semantics of graphically designed reconfigurable logic controller and serves as reference model for eventual further optimization efforts. It is considered that automatically generated array structure of logiccontroller is optimized for synthesis by professional tools. The most useful aspect for presented purposes is the ability to execute a VHDL behavioral specification closely related with array-based implementation. Even if the final implementation is not optimized during the logic synthesis process, it is compact, easy to modify and efficient.
The paper presents two different approaches to optimising operation speed of Programmable logiccontrollers. First approach optimizes architecture of the CPU and the program execution. It shows the two processors bit-...
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The paper presents two different approaches to optimising operation speed of Programmable logiccontrollers. First approach optimizes architecture of the CPU and the program execution. It shows the two processors bit-byte architecture which support of concurrent execution of bit and byte computation tasks. Second approach bases on hardware implemented control algorithm in reconfigurable platform based on FPGA. In second solution high performance is achieved by fully concurrent hardware execution of algorithm. Specific implementation tools enables typical PLC programming for hardware target platform.
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