With low-density parity-check (LDPC) code and polar code selected as the standard codes for 5 G eMBB scenario, one challenge is how to improve the hardware efficiency when both decoders are required by one system. Sin...
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ISBN:
(纸本)9781538648810
With low-density parity-check (LDPC) code and polar code selected as the standard codes for 5 G eMBB scenario, one challenge is how to improve the hardware efficiency when both decoders are required by one system. Since LDPC and polar codes can be decoded with belief propagation (BP) algorithms, this similarity allows us to design a reconfigurable decoder, which can decode both codes at the cost of only one decoder. Numerical and implementation results are also given in this paper to show that the proposed decoder achieves higher hardware efficiency than stand-alone LDPC or polar decoder, without harming the error performance.
A Raptor code is a concatenation of a fixed rate precode and a Luby-Transform ( LT) code that can be used as a rateless error-correcting code over communication channels. By definition, Raptor codes are characterized ...
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A Raptor code is a concatenation of a fixed rate precode and a Luby-Transform ( LT) code that can be used as a rateless error-correcting code over communication channels. By definition, Raptor codes are characterized by irregularity features such as dynamic rate, check-degree variability, and joint coding, which make the design of hardware-efficient decoders a challenging task. In this paper, serial turbo decoding of architecture-aware Raptor codes is mapped into sequential row processing of a regular matrix by using a combination of code enhancements and architectural optimizations. The proposed mapping approach is based on three basic steps: ( 1) applying systematic permutations on the source matrix of the Raptor code, ( 2) confining LT random encoding to pseudo-random permutation of messages and periodic selection of rowsplitting scenarios, and ( 3) developing a reconfigurable parallel check-node processor that attains a constant throughput while processing LT-and LDPC-nodes of varying degrees and count. The decoder scheduling is, thus, made simple and uniform across both LDPC and LT decoding. A serial decoder implementing the proposed approach was synthesized in 65 nm, 1.2 V CMOS technology. Hardware simulations show that the decoder, decoding a rate-0.4 code instance, achieves a throughput of 36 Mb/ s at SNR of 1.5 dB, dissipates an average power of 27 mW and occupies an area of 0.55 mm2.
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