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An Area Efficient and Low Power Consumption of Run Time Digital System Based on Dynamic Partial reconfiguration

INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING 2020年第3期48卷 431-446页

作者： Ram, R. Saravana Saminathan, A. Gopi Prakash, S. Arun Anna Univ Univ Coll Engn Dindigul Dept Elect & Commun Engn Dindigul Tamil Nadu India NPR Coll Engn & Technol Dept Elect & Commun Engn Natham Tamil Nadu India Anna Univ Dept Elect & Commun Engn Univ Coll Engn Ramanathapuram Ramanathapuram Tamil Nadu India

Digital signal processing besides multimedia applications needs plenty of data, real-time processing capacity, and high computational power. Thus, adaptable architectures with run-time reconfiguration abilities have gotten expanded consideration. Basically, reconfiguration computing is going towards advancing the application adaptability at runtime. A reconfigurable structure can be attained by working up the strategy aimed at configuring an array of programmable logic reprogramming. Field Programmable Gate Arrays (FPGAs) is made with the intention of reconfiguring the array system with interconnects as well as the configuration of logic blocks. To implement a high-performance FPGA device and also to enhance, the given paper proposes a proficient design strategy. The proposed strategy count upon the employment of dynamic partial reconfiguration (DPR) to drive from one mode then onto the next utilizing time-multiplexing on the same chip region. Furthermore, reconfigure modules to spare considerable area and enable the low-cost FPGAs usage. In the given work, reconfigurations of the modules accompanied by the memory are finished. The DPR is implemented betwixt these modes to shift from one mode then onto the next. The proposed method helps in diverse applications with various demands and also attains high performance, power consumption together with throughput. The proposed work gives improved performance with fewer powers and less area utilization which is illustrated by the Experimental outcomes.

关键词： Digital signal processing reconfiguration computing Field programmable gate array Dynamic partial reconfiguration

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