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IEEE DESIGN & TEST 2025年第2期42卷 79-88页

作者： Xie, Guihui Wang, Zijian Zhang, Yunxin Li, Ruyan Liu, Xin China Univ Geosci Sch Automat Wuhan 430072 Peoples R China Hubei Univ Sch Artificial Intelligence Wuhan 430062 Peoples R China Wuchang Shouyi Univ Sch Informat Sci & Engn Wuhan 430064 Peoples R China Wuhan Qingchuan Univ Sch Elect Informat Wuhan 430200 Peoples R China

Editor's notes: This article presents a compact and efficient five-stage pipeline RISC-V microprocessor by incorporating architectural optimization techniques for IoT applications. -Hiroki Matsutani, Keio Universi... 详细信息

关键词： Program processors Pipelines Read only memory Internet of Things Microprocessors Optimization Micromechanical devices reduced instruction set computing Logic Clocks RISC-V Five-stage Pipeline instruction Fetch Memory Access

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Shared Recurrence Floating-Point Divide/Sqrt and Integer Divide/Remainder With Early Termination

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IEEE TRANSACTIONS ON COMPUTERS 2025年第2期74卷 740-748页

作者： Kim, Kevin Parry, Katherine Harris, David Turek, Cedar Maiuolo, Alessandro Thompson, Rose Stine, James Harvey Mudd Coll Claremont CA 91711 USA Carnegie Mellon Univ Pittsburgh PA 15213 USA Oklahoma State Univ Stillwater OK 74078 USA

Division, square root, and remainder are fundamental operations required by most computer systems. Floating-point and integer operations are commonly performed on separate datapaths. This paper presents the first detailed implementation of a shared recurrence unit that supports floating-point division/square root and integer division/remainder. It supports early termination and shares the normalization shifter needed for integer and subnormal inputs. Synthesis results show that shared double-precision dividers producing at least 4 bits per cycle are 9 - 18% smaller and 3 - 16% faster than separate integer and floating-point units.

关键词： Optical wavelength conversion Hardware Logic Computers Approximation algorithms Adders Art Three-dimensional displays reduced instruction set computing Computer architecture Division square root remainder SRT early termination

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Comprehensive Investigation of Thermal and Mechanical Loads on Stator Winding Insulation in Nonsalient Synchronous Generator Under RISC Fault

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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT 2025年 74卷

作者： Sun, Kai He, Yu-Ling Chen, Hui-Cai Wu, Xue-Wei Yang, Jia-Wen Tang, Guiji Zhang, Fengyu Gerada, David North China Elect Power Univ Dept Mech Engn Baoding 071003 Peoples R China Univ Nottingham Dept Elect & Elect Engn Nottingham NG7 2RD England

Current studies on frequent rotor interturn short circuits (RISCs) primarily focus on fault diagnosis. However, the detrimental effect of RISC on the fragile stator winding insulation of synchronous generators is overlooked. Consequently, this article comprehensively investigates thermal and mechanical loads, as well as the structural responses of the stator winding insulation. The impact of RISC fault on the thermal and mechanical degradation distribution patterns of the insulation is explored in detail. Besides, different from the current research on RISC, this study considers a broader range of influencing factors, including degree, position, contact resistance, and output. In this article, detailed theoretical models for calculating thermal and mechanical loads are presented. Finite element analysis (FEA) and experiments are conducted on a 5-kW synchronous generator to calculate and test thermal and mechanical loads on the insulation. The mechanical, thermal, and coupling structural responses of the insulation are obtained and compared. The results indicate that maximum insulation structural responses caused by mechanical loads, thermal loads, and coupling actions are most pronounced at the nose end and the junction between the straight and involute lines, warranting careful attention. This study offers a unified approach and a practical framework for extended insulation service life.

关键词： reduced instruction set computing Insulation Stator windings Windings Synchronous generators Rotors Thermal loading Circuits Air gaps Circuit faults No-salient synchronous generator rotor interturn short circuit (RISC) structural responses thermal and mechanical loads winding insulation

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Investigation and Practical Applications of Seismo-Electromagnetic Joint Exploration

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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT 2025年 74卷

作者： Qiao, Shuaiqing Wei, Yilin Liu, Xiaojun Zhang, Qisheng Liu, Lihua Ji, Yicai Wang, Shun Zhang, Qimao Chinese Acad Sci Aerosp Informat Res Inst Beijing Peoples R China Shandong Univ Finance & Econ Sch Stat & Math Jinan 250014 Peoples R China China Univ Geosci Sch Geophys & Informat Technol Beijing 100083 Peoples R China

With the advancement of deep Earth exploration and urban underground space detection, addressing the challenges posed by environmental complexity and increasing data acquisition accuracy are increasingly critical. Conventional geophysical exploration techniques and their associated networking approaches cannot fulfill contemporary exploration requirements. Herein, the fundamental principles and inherent connections between seismic exploration and electromagnetic exploration are analyzed by comparing the circuit design for seismic and electromagnetic data-acquisition systems. Consequently, a technical solution for a seismo-electromagnetic joint acquisition system with high accuracies in both seismic and electromagnetic explorations is developed. A real-time host monitoring system is developed for both personal computers and mobile terminals. Moreover, a distributed hybrid networking scheme for this distributed seismo-electromagnetic high-accuracy acquisition system that incorporates wired, wireless, and self-storage intelligent arbitrary clipping is innovatively implemented, achieving a synchronization accuracy of <100 ns among various acquisition systems. The developed system is used for networking deployment in Zhangjiakou (Hebei, China), verification of key indicators in a coal mine with a depth of 848 m in Huainan (Anhui, China), and practical onsite explorations in Changzhi (Shanxi, China). The experimental and application results verify the reliability, stability, and practicality of the system. The proposed joint exploration technique fully leverages the advantages of distributed data-acquisition systems and can potentially shed light on the development of other joint research methodologies. The findings can increase the efficiency and accuracy of joint geophysical explorations, providing a solid foundation with regard to both machinery and technical aspects.

关键词： Electromagnetics Instruments Reflection Earth Electromagnetic scattering Wireless communication reduced instruction set computing Monitoring Hardware Accuracy Electromagnetic exploration high accuracy hybrid networking joint acquisition seismic exploration

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Implementation Research of Tiny ML on RISC-V Platform Using Efinix Platform for Real Time Person Detection

Implementation Research of Tiny ML on RISC-V Platform Using ...

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International Colloquium on Signal Processing & Its Applications, CSPA

作者： Yeap Wei Hao Cheong Choon Min Roslee Mohd Sabri Richard Lai Tian Fat Su Hsiao Wei Hazwan Halim Solahuddin Yusuf Fadhlullah School of Engineering INTI international College Penang Bayan Lepas Pulau Penang Malaysia MIMOS Berhad Technology Park Malaysia Bukit Jalil Kuala Lumpur Malaysia

ISBN: (数字)9798331522193

ISBN: (纸本)9798331522209

The rapid advancements in artificial intelligence (AI) and computer vision have revolutionized intelligent security systems, addressing challenges related to cost, efficiency, and scalability. This paper investigates the application of Tiny Machine Learning (TinyML) on the RISC-V platform, utilizing the Efinix Ti60 F225 FPGA for real-time person detection. The study aims to harness the energy efficiency, flexibility, and scalability of the RISC-V architecture to develop a cost-effective and sustainable solution for intelligent security applications. The proposed system combines the YOLO model for person detection with TinyML techniques, enabling real-time processing while maintaining an accuracy of 80% for individuals within a 2-meter range. Hardware components, such as the Raspberry Pi Camera Module V2 and Mini DSI Panel, were employed to capture and display real-time imagery. Comprehensive evaluations demonstrated the system's performance advantages, including reduced latency, low power consumption, and minimal bandwidth usage, emphasizing the benefits of deploying AI at the edge. Although challenges such as environmental variability and memory limitations were encountered, the findings highlighted the potential of integrating TinyML with RISC-V platforms for intelligent security applications. The results contributed to the field of edge computing and open-source hardware, presenting a viable approach to energy-efficient and scalable AI solutions. Future research will focus on overcoming hardware constraints, extending the detection range, and incorporating adaptive learning capabilities to enhance system robustness and functionality further.

关键词： YOLO reduced instruction set computing Costs Tiny machine learning Scalability Real-time systems Energy efficiency Security Artificial intelligence Field programmable gate arrays

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Microwave Photonics Computational Signal Algebra Framework for Radar Integrated Sensing and Communication Applications

Microwave Photonics Computational Signal Algebra Framework f...

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IEEE MTT-S Latin America Microwave Conference (LAMC)

作者： Cesar Aceros Juan Valera-Marquez Yvonne Aviles Domingo Rodriguez UTS Santander Colombia Universidad de Puerto Rico Río Piedras Universidad de Puerto Rico Mayagüez

ISBN: (数字)9798331540401

ISBN: (纸本)9798331540418

This work presents a computational signal algebra (CSA) framework for microwave photonics signal processing efforts in radar integrated sensing and communication (RISC) applications, for areas such as parameter estimation, beamforming, and waveform design. The proposed framework presents a set of computational methods, with an associated visualization environment for time-frequency tools such as the short-time Fourier transform (STFT), the cross-ambiguity function (CAF), and the Wigner-Ville distribution (WVD). The discrete ambiguity function (DAF) was implemented as a user defined function (UDF) to be used as a signal correlation analysis and waveform design tool aiming at assisting in research efforts towards efficient use of the electromagnetic spectrum by reducing noise and interference and adhering to spectrum management regulatory standards. Significant computational speedups were obtained for the CAF by introducing novel data sampling algorithmic techniques. Finally, an information flow security framework is proposed utilizing a post-quantum cryptography (PQC) approach in RISC environments.

关键词： Microwave measurement reduced instruction set computing Radar measurements Algebra Microwave communication Microwave theory and techniques Integrated sensing and communication Radar signal processing Cryptography Microwave photonics

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RISC-V: Redefining the Future of computing, Architecture, Innovations, and Beyond

RISC-V: Redefining the Future of Computing, Architecture, In...

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International Conference on Electronics, Materials Engineering and Nano-Technology (IEMENTech)

作者： Ankit P. Navik Sachin Kumar Tiwari Vipin Anand Brijesh Yadav Jonglae Park Ha Jun Sung System LSI Samsung Semiconductor India Research Bengaluru India System LSI Samsung Electronics Gyeonggi-do Republic of Korea

ISBN: (数字)9798331520762

ISBN: (纸本)9798331520779

In recent years, RISC-V has gained significant popularity and RISC-V computing device is going to increase by 2030 due to open-source and royalty-free instruction set architecture (ISA). RISC-V is widely adopted as an ISA for embedded processors globally. India has launched the Digital India RISC-V (DIR-V) program for next generation microprocessors in 2022, and many organizations have started working on the RISC-VISA. The RISC-V standards organization consistently introduces new ISA extensions to cater to the evolving requirements of advanced computing. The widespread of use of Android/Wear OS is attributed to technological advancements and the availability of cost-effective solutions for mobile and wearable devices. There are many operating systems are available for embedded devices such as iOS, Android, Tizen and FireFox. Among all of these OS Android is one of the most popular OS for wide variety of devices such as smartphones, wearable, automotive, smart TV, etc. In this paper, we present the study of RISC vs RISC-V. Further, the details of challenges to run operating system especially linux kernel based OS on RISC-V is covered.

关键词： Technological innovation reduced instruction set computing Smart TV Operating systems Standards organizations Organizations Wearable devices Smart phones Assembly Next generation networking

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Design and Performance Evaluation of RISC-V Embedded Processor Using HDL

Design and Performance Evaluation of RISC-V Embedded Process...

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Advances in Computer Science, Electrical, Electronics, and Communication Technologies (CE2CT), International Conference on

作者： Malhar Trivedi Akshit Mathur Kartik Mehta University of Southern California Los Angeles CA USA Pandit Deendayal Energy University Ahmedabad Gujarat India

ISBN: (数字)9798331518578

ISBN: (纸本)9798331518585

Today's world has seen the dawn of a new era with a sudden spike of interest much towards generative AI and Machine Learning throughout the globe and with computational powers beginning to show their might, we need fast and efficient microprocessors. To achieve higher efficiency, modern processors often adopt the RISC (reduced instruction set Computer) design principle, which emphasizes a smaller and simpler set of instructions, each executive in a uniform amount of time. In this research, we have tried to deploy a 5-stage pipelined general-purpose microprocessor architecture that achieves a clock period of 0.59 nanoseconds, translating to an operational frequency of 1.69 GHz through the implementation of optimization techniques in Verilog code. Additionally, the use of True Single- Phase Clocking (TSPC) flip-flops reduce the transistor count per flip-flop by approximately 50%, leading to a 20% decrease in overall power consumption. This paper highlights the application of RISC-V embedded processor design in obtaining a n-stage pipelined architecture for a general-purpose microprocessor using Verilog HDL on ModelSim and Xilinx.

关键词： reduced instruction set computing Power demand Microprocessors Computational modeling Computer architecture Central Processing Unit Registers Computational efficiency Hardware design languages Flip-flops

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Design, Analysis and Verification of AMBA AXI4.0

Design, Analysis and Verification of AMBA AXI4.0

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Visual Analytics and Data Visualization (ICVADV), International Conference on

作者： Aashima Lalit Mohan Saini School of VLSI and Embedded System Design National Institute of Technology Kurukshetra Haryana India Department of Electrical Engineering National Institute of Technology Kurukshetra Haryana India

ISBN: (数字)9798331521394

ISBN: (纸本)9798331521400

AMBA AXI was developed by ARM in 2003 upgrading it to AMBA AXI 4.0 in 2014. AMBA AXI4.0 is a fast, efficient, high frequency, high performance, high bandwidth SOC (system-on-chip) protocol that is used for communication between CPU (central processing unit) and FPGA (field programmable gate arrays). It has five communication channels for reading and writing between master and slave. It supports burst transactions and has handshake mechanism, which makes it suitable for high data transfers rate and for pipeline processing of instructions. It finds applications in various ARM (advanced RISC (reduced instruction set computer) machine) based FPGAs like Zynq-7000, Zynq Ultrascale+, Spartan 7, Arria 10 etc. This work implements the AXI4.0 protocol for communication between master and slave for 32 bits of data transfer and verification of using protocol checker.

关键词： reduced instruction set computing Visual analytics Communication channels Writing Data transfer Main-secondary Central Processing Unit System-on-chip Field programmable gate arrays Pipeline processing

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Investigating FPGA Gaming Systems: Real-Time Tic-Tac-Toe with Custom RISC, VGA Output, and Hardware Counters

Investigating FPGA Gaming Systems: Real-Time Tic-Tac-Toe wit...

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Trends in Material Science and Inventive Materials (ICTMIM), International Conference on

作者： C Saravanakumar Mohanakrishnan E Manoj Kumar D Jayasri K Jobitha Lakshmi J Department of ECE SRM Valliammai Engineering College Potheri India

ISBN: (数字)9798331501488

ISBN: (纸本)9798331501495

This paper presents an FPGA based real-time Tic Tac Toe gaming system with custom RISC processor, VGA output and hardware counters. In contrast, software-based implementation in traditional gaming systems can incur processing delays and increase resource overhead. We address these challenges in this research by developing a fully hardware-based solution that exploits parallelism and efficient resource utilization. With the proposed system, the behavior of latency and hardware utilization is optimized so that real time gameplay is with minimal latency. Synthesis and simulation confirm the implementation with low resource usage without compromising the smooth performance. The results validate the correctability of the approach based on using the FPGA for delivering it with interactive gaming experience with high responsiveness.

关键词： reduced instruction set computing Scalability Games Touch sensitive screens Rendering (computer graphics) Real-time systems Hardware Delays Resource management Field programmable gate arrays

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