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IEEE SPECTRUM 2000年第5期37卷 26-33页

作者： Geppert, L Perry, TS

It took Transmeta engineers $100 million, five years of secret toil, and a little magic to create fast low-power chips that turn into x86s in a microsecond. Transmeta Corporation's Crusoe chips look nothing like Intel's Pentium processors. They do not even have a logic gate in common. They are smaller, consume between one-third and one-thirtieth the power (depending on the application), and implement none of the same instructions in hardware. However the Crusoe microprocessors can run the same software that runs on IBM PC-compatible personal computers with Pentium chips-for instance, Microsoft Windows or versions of Unix, along with their software applications. The paper describes the development of the Crusoe chips.

关键词： Marketing and sales Personal communication networks Computer architecture Contracts Remuneration Chip scale packaging Microprocessors reduced instruction set computing Hardware VLIW

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MICROCODE OPTIMIZATION - EXAMPLES AND APPROACHES

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IEEE SOFTWARE 1986年第4期3卷 59-68页

作者： VEGDAHL, SR Tektronix Laboratories

Firmware engineering strategies range from hand coding to the use of optimizing compilers. For fine-tuned microcode we often need the advantages of both ends of the spectrum.

关键词： Optimizing compilers Switches Microprogramming reduced instruction set computing

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NStrace: A bus-driven instruction trace tool for PowerPC microprocessors

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IBM JOURNAL OF RESEARCH AND DEVELOPMENT 1997年第3期41卷 331-344页

作者： Sandon, PA Liao, YC Cook, TE Schultz, DM MartindeNicolas, P IBM CORP MICROELECT DIV AUSTIN TX 78758 USA IBM CORP AS400 DIV ROCHESTER MN 55901 USA

NStrace is a bus-driven hardware trace facility developed for the PowerPC(R) family of superscalar RISC microprocessors. It uses a recording of activity on a target processor's bus to infer the sequence of instructions executed during that recording period. NStrace is distinguished from related approaches by its use of an architecture-level simulator to generate the instruction sequence from the bus recording. The generated trace represents the behavior of the processor as it executes at normal speed while interacting normally with its run-time environment. Furthermore, details of the processor state that are not generally available to other trace mechanisms can be provided by the architectural simulation. There are two main components to the process of generating bus-driven instruction traces: bus capture and trace generation. Bus capture is triggered by a call to a system program that puts a particular address on the bus, then establishes the initial state of the processor by a combination of writing out register values and invalidating caches. A logic analyzer records the bus activity, and from this a file of bus transactions is produced. Trace generation proceeds by driving a processor simulator with these bus transactions and recording the sequence of instructions that results. The processor simulator is an elaboration of that developed for the PowerPC Visual Simulator. We have successfully generated instruction traces for a mix of utility programs and real applications on several microprocessor platforms running several operating systems. The capacity of the bus recording hardware is two million transactions, yielding instruction traces with lengths of the order of one hundred million instructions. This trace facility has been used for a number of studies covering a range of performance issues involving software, hardware, and their interactions.

关键词： reduced instruction set computing

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AND NOW A CASE FOR MORE COMPLEX instruction setS

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COMPUTER 1987年第9期20卷 71-83页

作者： FLYNN, MJ MITCHELL, CL MULDER, JM Stanford University

RISC-type designs are evaluated and compared with non-RISC instruction-set extensions using a level playing field with similar compiler strategies, without compatibility considerations, and with similar implementation constraints. instruction set evaluation is also considered. The data presented are based on five benchmark programs, which are also discussed.

关键词： Computer aided software engineering instruction sets reduced instruction set computing Runtime Computer aided instruction Vocabulary Optimizing compilers Operating systems Appraisal Computer architecture

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EVOLUTION OF THE POWERPC ARCHITECTURE

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IEEE MICRO 1994年第2期14卷 34-49页

作者： DIEFENDORFF, K OEHLER, R HOCHSPRUNG, R APPLE COMP INC DIV MACINTOSH HARDWARECUPERTINOCA

The PowerPC is a new RISC architecture derived from IBM's POWER architecture. The changes made to POWER simplify implementations, increase clock rates, enable a higher degree of superscalar execution, extend the architecture to 64 bits, and add multiprocessor support. For compatibility with existing software, the developers retained POWER's basic instruction set, opcode assignments, and programming model.

关键词： Computer architecture reduced instruction set computing Pipelines Delay Clocks Software performance Power system modeling Power generation Computer aided instruction High performance computing

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High-performance RISC microprocessors

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IEEE MICRO 1999年第4期19卷 48-55页

作者： Choquette, J Gupta, M McCarthy, D Veenstra, J SandCraft Inc Santa Clara CA 95054 USA

TWO MIPS CORES BASED ON THE MONTAGE ARCHITECTURE SUPPORT THE NEEDS OF EMBEDDED SYSTEMS ANO CONSUMER APPLIANCES. THE FLEXIBILITY OF THE ARCHITECTURE PERMITS EXTENSIONS TO BE RAPIDLY IMPLEMENTED TO MEET DEMANDING CUSTOM... 详细信息

关键词： reduced instruction set computing Microprocessors Pipelines Intellectual property Embedded system Costs Coprocessors Home appliances Integrated circuit modeling Lifting equipment

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MULTISTACK OPTIMIZATION FOR DATA-PATH CHIP LAYOUT

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1991年第1期10卷 116-129页

作者： LUK, WK DEAN, AA IBM CORP DIV GEN TECHNOLESSEX JUNCTIONVT 05452

A special multistack structure and optimization technique to partition, place, and wire the data-path macros in the form of the multistack structure are described, taking into account the connectivity of all the chip logic (data path, control logic, chip drivers, on-chip memory). The overall objective is: to fit the circuits within the chip boundary; to ensure data-path internal wirability; as well as external stack wirability to the other circuits; and to minimize wire lengths for wirability and timing. A tool for automatic multistack optimization has been implemented and applied successfully to layout high-density data path chips.< >

关键词： Logic Microprocessors Wiring Wire Very large scale integration reduced instruction set computing Driver circuits Timing Design automation Registers

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THE MIPS-R3010 FLOATING-POINT COPROCESSOR

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IEEE MICRO 1988年第3期8卷 53-62页

作者： ROWEN, C JOHNSON, M RIES, P MIPS Computer Systems Inc. USA

A description is given of the R3010 floating-point accelerator chip, a coprocessor that is based on advanced reduced-instruction-set-computer (RISC) architecture and VLSI design techniques and provides high-speed floating-point operation. The 75000-transistor hard-wired chip executes four instructions in parallel. Its performance is compared with that of available floating-point processors and its architecture is examined. The organization and implementation of the R3010 is discussed.

关键词： Coprocessors Very large scale integration reduced instruction set computing Floating-point arithmetic Delay Computer architecture Registers Hardware Systems engineering and theory Application software

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A CASE FOR DIRECT-MAPPED CACHES

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COMPUTER 1988年第12期21卷 25-40页

作者： HILL, MD Computer Sciences Department University of Wisconsin Madison Madison WI USA

Direct-mapped caches are defined, and it is shown that trends toward larger cache sizes and faster hit times favor their use. The arguments are restricted initially to single-level caches in uniprocessors. They are then extended to two-level cache hierarchies. How and when these arguments for caches in uniprocessors apply to caches in multiprocessors are also discussed.

关键词： Computer aided software engineering Central Processing Unit reduced instruction set computing Costs Hardware Capacitive sensors Read-write memory Computer aided instruction Sun

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Introducing KeyRing self-timed microarchitecture and timing-driven design flow

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IET COMPUTERS AND DIGITAL TECHNIQUES 2021年第6期15卷 409-426页

作者： Fiorentino, Mickael Thibeault, Claude Savaria, Yvon Polytech Montreal Dept Elect Engn Montreal PQ H3T 1J4 Canada Ecole Technol Super Dept Elect Engn Montreal PQ Canada

A self-timed microarchitecture called KeyRing is presented, and a method for implementing KeyRing circuits compatible with a timing-driven electronic design automation (EDA) flow is discussed. The KeyRing microarchitecture is derived from the AnARM, a low-power self-timed ARM processor based on ad hoc design principles. First, the unorthodox design style and circuit structures are revisited. A theoretical model that can support the design of generic circuits and the elaboration of EDA methods is then presented. Also addressed are the compatibility issues between KeyRing circuits and timing-driven EDA flows. The proposed method leverages relative timing constraints to translate the timing relations in a KeyRing circuit into a set of timing constraints that enable timing-driven synthesis and static timing analysis. Finally, two 32-bit RISC-V processors are presented;called KeyV and based on KeyRing microarchitectures, they are synthesized in a 65 nm technology using the proposed EDA flow. Postsynthesis results demonstrate the effectiveness of the design methodology and allow comparisons with a synchronous alternative called SynV. Performance and power consumption evaluations show that KeyV has a power efficiency that lies between SynV with clock-gating and SynV without clock-gating.

关键词： reduced instruction set computing design methodology Electrical/electronic equipment (energy utilisation) RISC-V processors circuit structures Logic and switching circuits Microprocessor chips design principles timing-driven electronic design automation flow low-power self-timed ARM processor relative timing constraints low-power electronics electronic design automation timing-driven synthesis asynchronous circuits circuit compatibility power efficiency Microprocessors and microcomputers Electronic engineering computing Logic circuits timing size 65.0 nm timing-driven EDA timing-driven design flow KeyRing circuit integrated circuit design static timing analysis KeyRing self-timed microarchitecture clock-gating KeyV processor Digital circuit design, modelling and testing microprocessor chips EDA flow word length 32 bit

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