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20-Bit RISC and DSP System Design in an FPGA

computing IN SCIENCE & ENGINEERING 2014年第2期16卷 16-20页

作者： Tomar, Amit Kumar Singh Jain, Rita Lakshmi Narain College of Technology India Lakshmi Narain College of Technology India

Today, most microprocessor and microcontroller designs are based on a reduced instruction set Computer core with several operations performed by a digital signal processor system. Here, the design of a RISC and DSP system is presented that uses very high-density logic (VHDL) and a field-programmable gate array (FPGA). This RISC is a 20-bit processor.

关键词： reduced instruction set computing Field Programmable Gate Arrays Registers Discrete Cosine Transforms Discrete Fourier Transforms Digital Signal Processing Logic Gates Scientific computing Arithmetic Logic Unit ALU CPU Control Unit CU Field Programmable Gate Array FPGA General Purpose Register GPR instruction Register IR Program Counter PC reduced instruction set Computer RISC Register set RS Multiply And Accumulates MA Cs Very Large instruction Word VLIW

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Microprocessor at 50: A Time to Celebrate and Energize for the Future INTRODUCTION

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IEEE MICRO 2021年第6期41卷 10-12页

作者： John, Lizy Kurian Narayanan, Vijaykrishnan Univ Texas Austin Elect & Comp Engn Dept Austin TX 78712 USA Penn State Univ Comp Sci & Engn & Elect Engn State Coll PA 16802 USA

The articles in this special section focus on the history and future technological development of microprocessors. Microprocessors have become more pervasive than any other landmark invention of the entire human civilization including the wheel, in spite of arriving a few millennia later. Many pioneers who have helped shape this amazing journey of microprocessors from its birth in 1971 to its omnipresence today share their perspectives in this special issue. Industry leaders in commemorating the special anniversary are keen to continue these innovations to an even greater extent and broader societal impact. It has been a remarkable journey from a few hundred transistors to new machine learning engines that occupy an entire wafer with more than a trillion transistors. The journey has had its share of drama and intense competition, both technical and legal. However, in this issue, the entire industry has come together to celebrate this landmark event for microprocessors.

关键词： Special Issues And Sections Microprocessors Program Processors reduced instruction set computing Performance Evaluation History Technology Forecasting

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EMULATING A COMPLEX instruction set COMPUTER WITH A reduced instruction set COMPUTER

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IEEE MICRO 1987年第1期7卷 60-72页

作者： MCNELEY, KJ MILUTINOVIC, VM PURDUE UNIV SCH ELECT ENGNW LAFAYETTEIN 47907

GaAs now allows up to 30K transistors per chip. With such a limitation, can you build a 32-bit CISC on a single GaAs chip? Yes, if you build a reduced instruction set computer and emulate the 32-bit CISC on it.

关键词： Computer aided instruction Gallium arsenide Silicon reduced instruction set computing Propagation delay Microprocessors Process design Military computing Temperature distribution Aerospace materials

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2001 NEEDS FOR MULTILEVEL INTERCONNECT TECHNOLOGY

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IEEE CIRCUITS AND DEVICES MAGAZINE 1995年第1期11卷 16-20页

作者： OH, SY CHANG, KJ Hewlett Packard Palo Alto CA Hewlett-Packard Co. Palo Alto CA USA

Looks at the materials and thermal alternatives for scaled, next-century VLSI/ULSI interconnects. It is shown that ad hoc executions of programs to calculate interconnect parameters for VLSI/ULSI design and analysis are too time-consuming to be practical. The tool used in this study to model a hypothetical interconnect system was Hewlett Packard's HTVE (HP Interconnect Value Extractor).< >

关键词： Integrated circuit interconnections Clocks Capacitance Frequency reduced instruction set computing Microprocessors Ultra large scale integration Delay lines Routing Crosstalk

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THERMAL MODELING AND EXPERIMENTAL CHARACTERIZATION OF THE C4 SURFACE-MOUNT-ARRAY INTERCONNECT TECHNOLOGIES

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IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY PART A 1995年第1期18卷 87-93页

作者： KROMANN, GB MOTOROLA INC MICROPROCESSOR MEMORY & TECHNOL GRPADV PACKAGING TECHNOLAUSTINTX 78735

This paper presents various thermal management options available for controlled collapse chip connection (C4) die attached to a ceramic surface mount array (SMA) substrate, as they apply to low end/midrange computer products, The Motorola 88110 RISC microprocessor was used as a thermal test vehicle to verify theoretical models, for a limited set of boundary conditions, A thermal test board was designed to accommodate the 25 mm substrate and its use will be discussed, The focus is the internal package resistance and the effects of parameters such as: the C4 bumps, the thermal paste, and the thermal paste thickness, However, the die junction-to-ambient resistance is presented for attached commercially-available heat sinks convectively cooled (to 4 m/s) for typical workstation computer-systems operational constraints.

关键词： Thermal resistance Thermal management Testing Ceramics reduced instruction set computing Microprocessors Vehicles Boundary conditions Packaging Resistance heating

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A 120-MHZ BICMOS SUPERSCALAR RISC PROCESSOR

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1994年第4期29卷 389-396页

作者： TANAKA, S HOTTA, T MURABAYASHI, F YAMADA, H YOSHIDA, S SHIMAMURA, K KATSURA, K BANDOH, T IKEDA, K MATSUBARA, K SAITOU, K NAKANO, T SHIMIZU, T SATOMURA, R HITACHI LTD DIV GEN PURPOSE COMPHITACHIIBARAKI 31912JAPAN HITACHI LTD CTR DEVICE DEVHITACHIIBARAKI 31912JAPAN

A superscalar RISC processor contains 2.8 million transistors in a die size of 16.2 mm x 16.5 mm, and utilizes 3.3 V/0.5 pm BiCMOS technology. In order to take advantage of superscalar performance without incurring penalties from a slower clock or a longer pipeline, a tag bit is implemented in the instruction cache to indicate dependency between two instructions. A performance gain of up to 37% is obtained with only a 3.5% area overhead from our superscalar design.

关键词： BiCMOS integrated circuits reduced instruction set computing Pipelines CMOS technology Integrated circuit technology Processor scheduling Clocks Process design Microarchitecture Performance gain

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Exact and approximate algorithms for the extension of embedded processor instruction sets

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2006年第7期25卷 1209-1229页

作者： Pozzi, Laura Atasu, Kubilay Ienne, Paolo Ecole Polytech Fed Lausanne Sch Comp & Commun Sci CH-1015 Lausanne Switzerland

In embedded computing, cost, power, and performance constraints call for the design of specialized processors, rather than for the use of the existing off-the-shelf solutions. While the design of these application-specific CPUs could be tackled from scratch, a cheaper and more effective option is that of extending the existing processors and toolchains. Extensibility is indeed a feature now offered in real designs, e.g., by processors such as Tensilica Xtensa [T. R. Halfhill, Microprocess Rep., 20031, ARC ARCtangent [T. R. Halfhill, Microprocess Rep., 20001, STMicroelectronics ST200 [P. Faraboschi, G. Brown, J. A. Fisher, G. Desoli, and F. Homewood, Proc. 27th Annu. Int. Symp. Computer Architecture, 2000, p. 203], and MIPS CorExtend [T. R. Halfhill, Microprocess Rep., 2003]. While all these processors provide development environments with simulation capabilities for evaluating efficiently hand-crafted solutions, the tools to identify automatically the best processor configuration for a given application are less common. In particular, solutions to choose specialized instruction-set extensions (ISEs) have been investigated in the past years but are still seldom part of commercial toolchains. This paper provides a formal methodology and a set of algorithms that help address the problem. It proposes exact algorithms to derive optimal ISEs;exact identification of a single ISE is applicable to basic blocks of up to 1500 assembler-like instructions. This paper also introduces approximate methods that can process basic blocks of larger size. Results show that the described algorithms find solutions close to those that a designer would obtain by a detailed study of the application code. Both heuristic and exact algorithms find ISEs able to speed up unextended processors up to 5.0x. State-of-the-art comparisons show that the presented algorithms outperform existing ones by up to 2.6x.

关键词： application-specific microprocessors computer instructions customizable microprocessors extensible microprocessors instruction-set extensions reduced instruction set computing tightly-coupled coprocessors

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WAFER SCALE INTERCONNECTIONS FOR GAAS PACKAGING - APPLICATIONS TO RISC ARCHITECTURE

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COMPUTER 1987年第4期20卷 21-35页

作者： MCDONALD, JF GREUB, HJ STEINVORTH, RH DONLAN, BJ BERGENDAHL, AS Rensselaer Polytechnic Institute

A high-speed, high-density, wafer-scale packaging technology for the implementation of GaAs systems is described. The particular requirements of wafer-scale integrated (WSI) packaging and the difficulties involved are examined. The Tektronix-Triquint E/D foundry for producing 1. 0- mu m enhancement/depletion (E/D) MESFETs, is examined. The propagation delay and bandwidth of WSI interconnections are discussed, and fabrication and yield issues are considered.

关键词： Gallium arsenide Packaging reduced instruction set computing Silicon Wiring Integrated circuit interconnections Costs MESFETs Instruments MMICs

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OPERATION OF COMMERCIAL R3000 PROCESSORS IN THE LOW EARTH ORBIT (LEO) SPACE ENVIRONMENT

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 1991年第6期38卷 1415-1420页

作者： KASCHMITTER, JL SHAEFFER, DL COLELLA, NJ MCKNETT, CL COAKLEY, PG JAYCOR INC SANTA MONICACA

Spacecraft processors must operate with minimal degradation of performance in the Low Earth Orbit (LEO) radiation environment, which includes the effects of total accumulated ionizing dose and Single Event Phenomena (SEP) caused by protons and cosmic rays. Commercially available microprocessors can offer a number of advantages relative to radiation-hardened devices, including lower cost, reduced development and procurement time, extensive software support, higher density and performance. However, commercially available systems are not normally designed to tolerate effects induced by the LEO environment. Lawrence Livermore National Laboratory (LLNL) and others have extensively tested the MIPS R3000 reduced instruction set Computer (RISC) microprocessor family for operation in LEO environments. We have characterized total dose and SEP effects for altitudes and inclinations of interest to systems operating in LEO, and we postulate techniques for detection and alleviation of SEP effects based on experimental results.

关键词： Low earth orbit satellites Microprocessors Space vehicles Degradation Ionizing radiation Protons Cosmic rays Testing Computer aided instruction reduced instruction set computing

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An interconnect architecture for networking systems on chips

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IEEE MICRO 2002年第5期22卷 36-45页

作者： Karim, F Nguyen, A Dey, S STMicroelect Adv Syst Technol Adv Comp Lab San Diego CA 92121 USA Univ Calif San Diego Dept Elect & Comp Engn San Diego CA 92103 USA

Network processor systems on chips meet the speed and flexibility requirements of next-generation Internet routers. the octagon on-chip communication architecture, with its cost, performance, and scalability advantage... 详细信息

关键词： Network-on-a-chip System-on-a-chip Network synthesis Telecommunication traffic IP networks Web and internet services reduced instruction set computing Costs Scalability Protocols

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