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2012 International Conference on Solid State Devices and Materials Science(SSDMS 2012)

作者： Chenxu WANG Jiamin ZHENG Mingyan YU Microelectronics Center Harbin Institute of Technology at Weihai

The embedded processor performance is significantly influenced by cache whose performance depend on its architecture parameters. Meanwhile, In order to overcome the non-timing accurate flaw of software simulation method, In this paper, a hardware emulation method--RTL level models is used for CPU and cache controller, while circuit model for cache memory cell--is adopted to do research on cache performance. A more accurate design space, miss rate and cycle trend influenced by cache parameters, is presented. Compared with Round Robin, it shows that miss rate and cycle number of instruction cache is reduced by 22.08% and 20.36%, respectively, because PseudoLRU is adopted.

关键词： cache performance research hardware model replacement algorithm

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Towards a Flexible Resource Management System for Content Centric Networking

Towards a Flexible Resource Management System for Content Ce...

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IEEE International Conference on Communications

作者： Indra Widjaja Bell Labs Alcatel-Lucent

ISBN: (纸本)9781457720529

Content Centric Networking (CCN) is a new and promising architecture that can provide better security and much improved content delivery service than the current Internet. Each router in CCN has a content store that caches objects according to a replacement algorithm and a pending interest table that stores pending requests waiting for matching objects. We propose a novel and flexible resource management system where the content store can store objects as well as pending requests. To each pending request, we add control fields that can be used to control caching resources according to a given objective function. We examine several applications that can benefit from using the proposed resource management system. The experimental results quantify key performance improvements.

关键词： Resource Management System replacement algorithm Objective function shopping mall Networking Cache memory FLEXIBLE

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Improving Last-Level Cache performance by exploiting the concept of MRU-Tour

Improving Last-Level Cache performance by exploiting the con...

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20th International Conference on Parallel Architectures and Compilation Techniques, PACT 2011

作者： Valero, Alejandro Sahuquillo, Julio Petit, Salvador López, Pedro Duato, José Department of Computer Engineering Universitat Politècnica de València Valencia Spain

ISBN: (纸本)9780769545660

Last-Level Caches (LLCs) implement the LRU algorithm to exploit temporal locality, but its performance is quite far of Belady's optimal algorithm as the number of ways increases. One of the main reasons because of LRU does not reach good performance in LLCs is that this policy forces a block to descend until the bottom of the stack before eviction. Nevertheless, most of the blocks that leave the MRU position are not referenced again before eviction. This work pursues to select candidate blocks to be victimized before reaching the bottom of the stack. To this end, this work defines the number of MRU-Tours (MRUTs) of a block as the number of times that a block enters in the MRU position during its live time. Based on the fact that most of the blocks exhibit a single MRUT, this work presents the family of MRUT-based algorithms aimed at exploiting this block behavior to improve performance. © 2011 IEEE.

关键词： Belady optimal algorithm Benchmark testing Complexity theory Computers Hardware LRU algorithm Last-Level Cache MRU-Tour MRU-tour Parallel architectures cache storage last-level cache performance performance evaluation replacement algorithm

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Improving Networked File System Performance Using a Locality-Aware Cooperative Cache Protocol

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IEEE TRANSACTIONS ON COMPUTERS 2010年第11期59卷 1508-1519页

作者： Jiang, Song Zhang, Xuechen Liang, Shuang Davis, Kei Wayne State Univ Dept Elect & Comp Engn 5050 Anthony Wayne Dr Detroit MI 48202 USA Ohio State Univ Dept Comp Sci & Engn Columbus OH 43210 USA Los Alamos Natl Lab Los Alamos NM 87545 USA

In a distributed environment, the utilization of file buffer caches in different clients may greatly vary. Cooperative caching has been proposed to increase cache utilization by coordinating the shared usage of distributed caches. It allows clients that would more greatly benefit from larger caches to forward data objects to peer clients with relatively underutilized caches. To support such coordination, global cache utilization must be dynamically evaluated. This, in turn, requires an effective analysis of application data access patterns. Existing coordination protocols are demonstrably suboptimal in this respect, exhibiting inefficient memory utilization and undue interference among clients. We propose a locality-aware cooperative caching protocol, called LAC, that is based on analysis and manipulation of data block reuse distance to effectively predict cache utilization and the probability of data reuse at each client. Using a dynamically adaptive synchronization technique, we keep local information up to date and consistently comparable across clients. The system is highly scalable in the sense that global coordination is achieved without centralized control. We have conducted thorough trace-driven simulation experiments to assess the performance differences between LAC and various existing protocols representative of the general class. Using a realistic and representative cost model, we show that the LAC protocol significantly and consistently outperforms existing cooperative caching protocols, demonstrating high and balanced utilization of caches across all clients. In our experiments, LAC reduces block access time by up to 36 percent, with an average of 31 percent, over the system without peer cache coordination, and reduces block access time by up to 22 percent, with an average of 13 percent, over the best performer of the existing protocols.

关键词： replacement algorithm locality cooperative caching networked file system

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Pair of replacement algorithms MFMR and AF-LRU on L1 and L2 Cache for Proxy Server

Pair of Replacement Algorithms MFMR and AF-LRU on L1 and L2 ...

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2009 Annual IEEE India Conference

作者： Gupta, Richa Tokekar, Sanjiv Acropolis Inst Technol & Res Indore Madhya Pradesh India Inst Engn & Technol Elect & Telecom Engn Indore Madhya Pradesh India

ISBN: (纸本)9781424448586

Access to the internet and WWW is growing extensively, which results in heavy network traffic. To reduce the network traffic proxy server is used. Proxy server reduces the load of server. If the cache replacement algorithm of proxy server's cache is efficient then proxy server will be helpful to reduce the network traffic in more efficient manner. In this paper we are considering proxy server cache to be Level 1 (L1) cache and storage cache of proxy server to be Level 2 (L2) cache. For collecting the real trace proxy server is used in an organization. Log of proxy server gives the information of various URLs accessed by various clients with time. For performing experiments various URLs were given a numeric identity. This paper analyzes the behavior of various replacement algorithms. The replacement algorithms taken into consideration are Least Recently Used (LRU), Least Frequently Used (LFU), First In First Out (FIFO). This paper proposes a new replacement algorithm named MFMR (Most Frequent with Maximum Reusability) for L1 which works about 16% better than existing algorithms considered in this paper. This paper also proposes a new replacement policy for L2 named AF_LRU (Average Frequency, Least Recently Used). Simulation results shows that pair of MFMR and AF-LRU is approximately 28% better than other existing pairs of replacement algorithms considered.

关键词： Level 1 Cache (L1) Level 2 Cache (L2) web access pattern replacement algorithm Proxy server client

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An Aggregation Cache replacement algorithm Based on Ontology Clustering

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Wuhan University Journal of Natural Sciences 2006年第5期11卷 1141-1146页

作者： ZHU Jiang SHEN Qingguo TANG Tang LI Yongqiang Institute of Communications Engineering PLAUniversity of Science and Technology Nanjing. 210007Jiangsu China

This paper describes the theory, implementation, and experimental evaluation of an Aggregation Cache replacement （ ACR ） algorithm. By considering application background, carefully choosing weight values, using a special formula to calculate the similarity, and clustering ontologies by similarity for getting more embedded deep relations, ACR combines the ontology similarity with the value of object and decides which object is to be replaced. We demonstrate the usefulness of ACR through experiments. （a） It is found that the aggregation tree is created wholly differently according to the application cases. Therefore, clustering can direct the content adaptation more accurately according to the user perception and can satisfy the user with different preferences. （b） After comparing this new method with widely-used algorithm Last-Recently-Used （LRU） and First-in-First-out （FIFO） method, it is found that ACR outperforms the later two in accuracy and usability. （c） It has a better semantic explanation and makes adaptation more personalized and more precise.

关键词： ontology similarity replacement algorithm content adaptation semantic Web

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Cache Performance Research For Embedded Processors

Cache Performance Research For Embedded Processors

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2010 International Conference on Circuit and Signal Processing (ICCSP 2010) & 2010 Second IITA International Joint Conference on Artificial Intelligence (IITA-JCAI 2010)

作者： Chenxu WANG Jiamin ZHENG Mingyan YU Microelectronics Center Harbin Institute of Technology at Weihai Weihai, Shandong

The embedded processor performance is significantly influenced by cache whose performance depend on its architecture parameters. Meanwhile, In order to overcome the non-timing accurate flaw of software simulation method, In this paper, a hardware emulation method --RTL level models is used for CPU and cache controller, while circuit model for cache memory cell--is adopted to do research on cache performance . A more accurate design space, miss rate and cycle trend influenced by cache parameters, is presented. Compared with Round Robin, it shows that miss rate and cycle number of instruction cache is reduced by 22.08% and 20.36%, respectively, because Pseudo- LRU is adopted.

关键词： cache performance research hardware model replacement algorithm

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A ZERO-ONE LAW FOR RANDOM SUBGROUPS OF SOME TOTALLY DISCONNECTED GROUPS

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TRANSFORMATION GROUPS 2009年第4期14卷 787-800页

作者： Glasner, Yair Ben Gurion Univ Negev Dept Math IL-84105 Beer Sheva Israel

Let A be a locally compact group topologically generated by d elements and let k > d. Consider the action, by precomposition, of Gamma = Aut(F(k)) on the set of marked, k-generated, dense subgroups D(k,A) := {eta epsilon Hom(F(k,A))| <()over bar> = A}. We prove the ergodicity of this action for the following two families of simple, totally disconnected, locally compact groups: A = PSL(2)(K) where K is a non-Archimedean local field (of characteristic not equal 2);A = Aut(0)(T(q+1))| the group of orientation- preserving automorphisms of a q + 1 regular tree, for q >= 2. In contrast, a recent result of Minsky's shows that the same action fails to be ergodic for A = PSL(2)(C) and, when k is even, also for A = PSL(2)(R). Therefore, if k >= 4 is even and K is a local field (with char(K) not equal 2), the action of Aut(F(k)) on D(k,PSL2(K)) is ergodic if and only if K is non-Archimedean. Ergodicity implies that every "measurable property" either holds or fails to hold for almost every k-generated dense subgroup of A.

关键词： PRODUCT replacement algorithm DISTRIBUTING POINTS AUTOMORPHISM GROUP HECKE OPERATORS REGULAR TREES T-SYSTEMS PRESENTATIONS CONNECTIVITY GENERATORS GRAPH Action connectivity replacement algorithm

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The Challenge of Eliminating Storage Bottlenecks in Distributed Systems

The Challenge of Eliminating Storage Bottlenecks in Distribu...

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1st International Workshop on Software Technologies for Future Dependable Distributed Systems

作者： Ueda, Takanori Hirate, Yu Yamana, Hayato Waseda Univ Tokyo 1698555 Japan

ISBN: (纸本)9781424435654

One of the most difficult problems in distributed systems is load-balancing. Even if we take care of load-balancing, heavily-loaded nodes often occur while there are still lightly-loaded nodes that have idle memory and idle CPU power. Our idea is to exploit this idle memory and idle CPU power to improve the storage performance of heavily-loaded nodes. Idle memory can be used for caching file data and idle CPU power can be used for extracting file access patterns from file access logs. File access patterns are valuable sources for optimizing a cache strategy. Our project goal is to improve the overall performance of distributed systems by improving storage access performance. This paper gives an overview of this project idea and reports the current status of the project. In addition, we show benchmark results from our prototype cache extension system, which is implemented in Linux Kernel 2.6. The DBT-3 (TPC-H) benchmark results show that our system can increase computer speed by a factor of 6.68.

关键词： Access pattern Access pattern mining Buffer caching Distributed systems replacement algorithm

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Buffer Cache Management for Combined MLC and SLC Flash Memories Using both Volatile and Nonvolatile RAMs

Buffer Cache Management for Combined MLC and SLC Flash Memor...

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15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications

作者： Park, Junseok Bahn, Hyokyung Koh, Kern Seoul Natl Univ Sch Engn & Comp Sci Seoul South Korea Ewha Womans Univ Dept Comp Sci Seoul South Korea

ISBN: (纸本)9780769537870

This paper presents a new buffer cache management scheme called DABC-NV for mixed MLC and SLC flash memories as the secondary storage and both byte-accessible NVRAM and conventional volatile RAM as their buffer caches. DABC-NV has four salient features. First, it allocates buffer cache space to MLC and SLC flash memories based on their I/O costs and then dynamically adjusts the allocated size according to the evolution of workloads. Second, it separately exploits read and write histories of block references, and thus it estimates future references of each operation more precisely. Third, it guarantees the complete consistency of write I/Os since all dirty data are cached in nonvolatile buffer caches. Fourth, metadata lists are maintained separately from cached blocks. This allows more efficient management of volatile and nonvolatile buffer caches based on read and write histories, respectively. Trace-driven simulations show that DABC-NV improves the I/O performance of embedded systems significantly. Specifically, it reduces I/O time by 24% on average compared to the CLOCK-NV algorithm.

关键词： replacement algorithm NVRAM NAND flash memory buffer caching MLC flash memory

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