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IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Georgios Keramidas Pavlos Petoumenos Stefanos Kaxiras University of Patras Greece

ISBN: (纸本)9781424412570;1424412587

Several cache management techniques have been proposed that indirectly try to base their decisions on cacheline reuse-distance, like Cache Decay which is a postdiction of reuse-distances: if a cacheline has not been accessed for some ldquodecay intervalrdquo we know that its reuse-distance is at least as large as this decay interval. In this work, we propose to directly predict reuse-distances via instruction-based (PC) prediction and use this information for cache level optimizations. In this paper, we choose as our target for optimization the replacement policy of the L2 cache, because the gap between the LRU and the theoretical optimal replacement algorithm is comparatively large for L2 caches. This indicates that, in many situations, there is ample room for improvement. We evaluate our reusedistance based replacement policy using a subset of the most memory intensive SPEC2000 and our results show significant benefits across the board.

关键词： secondary memory replacement algorithm Cache memory cache replacement Subset metasomatism Surgical Replantation Decay Decay Decay decay Decay Alkali Disintegration biodeterioration

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Improving Last-Level Cache performance by exploiting the concept of MRU-Tour

Improving Last-Level Cache performance by exploiting the con...

引用

20th International Conference on Parallel Architectures and Compilation Techniques, PACT 2011

作者： Valero, Alejandro Sahuquillo, Julio Petit, Salvador López, Pedro Duato, José Department of Computer Engineering Universitat Politècnica de València Valencia Spain

ISBN: (纸本)9780769545660

Last-Level Caches (LLCs) implement the LRU algorithm to exploit temporal locality, but its performance is quite far of Belady's optimal algorithm as the number of ways increases. One of the main reasons because of LRU does not reach good performance in LLCs is that this policy forces a block to descend until the bottom of the stack before eviction. Nevertheless, most of the blocks that leave the MRU position are not referenced again before eviction. This work pursues to select candidate blocks to be victimized before reaching the bottom of the stack. To this end, this work defines the number of MRU-Tours (MRUTs) of a block as the number of times that a block enters in the MRU position during its live time. Based on the fact that most of the blocks exhibit a single MRUT, this work presents the family of MRUT-based algorithms aimed at exploiting this block behavior to improve performance. © 2011 IEEE.

关键词： Belady optimal algorithm Benchmark testing Complexity theory Computers Hardware LRU algorithm Last-Level Cache MRU-Tour MRU-tour Parallel architectures cache storage last-level cache performance performance evaluation replacement algorithm

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Honeywell :: Multics :: Redell :: Mtb :: Mtb-170

引用

2016年

Honeywell :: Multics :: Redell :: Mtb :: Mtb-170 by published by

关键词： algorithm device device map device records directory hierarchy drum honeywell main main memory memory mtb-170 multics paging paging device redell replacement algorithm secondary storage segment segment number segments storage virtual memory wait delay

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Honeywell :: Multics :: Haley :: an61 Ch5 Sep78

引用

2016年

Honeywell :: Multics :: Haley :: an61 Ch5 Sep78 by published by

关键词： bulk store control core map device device record disk haley honeywell interrupt side main main memory memory memory frame multics paging paging device ptw replacement algorithm rws segment sep78 sst table lock traffic controller

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ezswap: Enhanced Compressed Swap Scheme for Mobile Devices

引用

IEEE ACCESS 2019年 7卷 139678-139691页

作者： Kim, Jongseok Kim, Cheolgi Seo, Euiseong Sungkyunkwan Univ Dept Comp Sci & Engn Seoul 16419 South Korea Korea Aerosp Univ Dept Software & Comp Engn Goyang 10540 South Korea

The limited memory capacity of mobile devices leads to the popular use of compressed swap schemes, which reduce the I/O operations involving the swapping in and out of infrequently accessed pages. However, most of the current compressed swap schemes indiscriminately compress and store all swap-out pages. Considering that both energy and computing power are scarce resources in mobile devices, and modern applications frequently deal with already-compressed multimedia data, this blind approach may cause adverse impacts. In addition, they focus only on anonymous pages and not on file-mapped pages, because the latter are backed by on-disk files. However, our observations revealed that, in mobile devices, file-mapped pages consume significantly more memory than anonymous pages. Last but not least, most of the current compressed swap schemes blindly follow the least-recently-used (LRU) discipline when choosing the victim pages for replacement, not considering the compression ratio or data density of the cached pages. To overcome the aforementioned problems and maximize the memory efficiency, we propose a compressed swap scheme, called enhanced zswap (erswap), for mobile devices. erswap accommodates not only anonymous pages, but also clean file-mapped pages. It estimates the compression ratio of incoming pages with their information entropy, and selectively compresses and caches the pages only with beneficial compression ratios. In addition, its admission control and cache replacement algorithms are based on a cost-benefit model that considers not only the access recency of cached pages but also their information density and expected eviction cost. The proposed scheme was implemented in the Linux kernel for Android. Our evaluation with a series of commercial applications demonstrated that it reduced the amount of flash memory read by up to 55%, thereby improving the application launch time by up to 22% in comparison to the original zswap.

关键词： Compressed swap paging compression replacement algorithm memory management mobile devices

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Effective reference probability incorporating the effect of expiration time in Web cache

引用

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 2001年第9期E84D卷 1184-1197页

作者： Lee, JJ Whang, KY Moon, YS Hong, EK Korea Adv Inst Sci & Technol Dept Comp Sci Seoul 131 South Korea Korea Adv Inst Sci & Technol AITrc Seoul South Korea Seoul Natl Univ Dept Comp Sci & Stat Seoul South Korea

Web caching has become an important problem when addressing the performance issues in Web applications. The expiration time of the Web data item is useful a piece of information for performance enhancement in Web caching. In this paper, we introduce the notion of the effective reference probability that incorporates the. effect of expiration time for Web caching. For a formal approach, we propose the continuous independent reference model extending the existing independent reference model. Based on this model, we define formally the effective reference probability and derive it theoretically. By simply replacing the reference probability in the existing cache replacement algorithms with the effective reference probability, we can take the effect of expiration time into account. The results of performance experiments show that the replacement algorithms using the effective reference probability always outperform existing ones. In particular, when the cache fraction is 0.05 and data update is comparatively frequent (i.e., the update frequency is more than 1/10 of the reference frequency), the performance is enhanced by more than 30% in LRU-2 and 13% in Aggarwal's method. The results show that the effective reference probability significantly enhances the performance of Web caching when the expiration time is given.

关键词： replacement algorithm expiration time Web cache

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Combining Recency of Information with Selective Random and a Victim Cache in Last-Level Caches

引用

ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION 2012年第3期9卷 16-16页

作者： Valero, Alejandro Sahuquillo, Julio Petit, Salvador Lopez, Pedro Duato, Jose Univ Politecn Valencia Dept Comp Engn DISCA E-46071 Valencia Spain

Memory latency has become an important performance bottleneck in current microprocessors. This problem aggravates as the number of cores sharing the same memory controller increases. To palliate this problem, a common solution is to implement cache hierarchies with large or huge Last-Level Cache (LLC) organizations. LLC memories are implemented with a high number of ways (e.g., 16) to reduce conflict misses. Typically, caches have implemented the LRU algorithm to exploit temporal locality, but its performance goes away from the optimal as the number of ways increases. In addition, the implementation of a strict LRU algorithm is costly in terms of area and power. This article focuses on a family of low-cost replacement strategies, whose implementation scales with the number of ways while maintaining the performance. The proposed strategies track the accessing order for just a few blocks, which cannot be replaced. The victim is randomly selected among those blocks exhibiting poor locality. Although, in general, the random policy helps improving the performance, in some applications the scheme fails with respect to the LRU policy leading to performance degradation. This drawback can be overcome by the addition of a small victim cache of the large LLC. Experimental results show that, using the best version of the family without victim cache, MPKI reduction falls in between 10% and 11% compared to a set of the most representative state-of-the-art algorithms, whereas the reduction grows up to 22% with respect to LRU. The proposal with victim cache achieves speedup improvements, on average, by 4% compared to LRU. In addition, it reduces dynamic energy, on average, up to 8%. Finally, compared to the studied algorithms, hardware complexity is largely reduced by the baseline algorithm of the family.

关键词： Design Performance Last-Level Cache MRU-Tour replacement algorithm

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Efficient and tailored resource management for the p2p web caching

引用

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 2007年第1期E90D卷 48-57页

作者： Kim, Kyungbaek Park, Daeyeon Korea Adv Inst Sci & Technol Dept Elect Engn & Comp Sci Div Elect Engn Taejon 305701 South Korea

While web proxy caching is a widely deployed technique, the performance of a proxy cache is limited by the local storage. Some studies have addressed this limitation by using the residual resources of clients via a p2p method and have achieved a very high hit rate. However, these approaches treat web objects as homogeneous objects and there is no consideration of various web characteristics. Consequently, the byte hit rate of the system is limited, external bandwidth is wasted, and perceived user latency is increased. The present paper suggests an efficient p2p based web caching technique that manages objects with different policies so as to exploit the characteristics of web objects, such as size and temporal locality. Small objects are stored alone whereas large objects are stored by dividing them into numerous small blocks, which are distributed in clients. On a proxy cache, header blocks of large objects take the place of objects themselves and smaller objects are cached. This technique increases the hit rate. Unlike a web cache, which evicts large objects as soon as possible in the case where clients fulfill the role of backup storage, large objects are given higher priority than small objects in the proposed approach. This maximizes the effect of hits for large objects and thereby increases the byte hit rate. Furthermore, we construct simple latency models for various p2p based web caching systems and analyze the effects of the proposed policies on these systems. We then examine the performances of the efficient policies via a trace driven simulation. The results demonstrate that the proposed techniques effectively enhance web cache performance, including hit rate, byte hit rate, and response time.

关键词： peer-to-peer web caching replacement algorithm

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Cache Performance Research for Embedded Processors

引用

Physics Procedia 2012年 25卷 1322-1328页

作者： Chenxu Wang Jiamin Zheng Mingyan Yu Microelectronics Center Harbin Institute of Technology at WeihaiWeihai Shandong

The embedded processor performance is significantly influenced by cache whose performance depend on its architecture parameters. Meanwhile, In order to overcome the non-timing accurate flaw of software simulation method, In this paper, a hardware emulation method --RTL level models is used for CPU and cache controller, while circuit model for cache memory cell--is adopted to do research on cache performance. A more accurate design space, miss rate and cycle trend influenced by cache parameters, is presented. Compared with Round Robin, it shows that miss rate and cycle number of instruction cache is reduced by 22.08% and 20.36%, respectively, because Pseudo- LRU is adopted.

关键词： cache performance research hardware model replacement algorithm

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The Configuration Strategies on Caching for Web Servers

引用

Wuhan University Journal of Natural Sciences 2006年第3期11卷 585-590页

作者： GUO Chengcheng ZHANG Li YAN Puliu School of Electronic Information Wuhan UniversityWuhan 430072 Hubei China

The Web cluster has been a popular solution of network server system because of its scalability and cost effective ness. The cache configured in servers can result in increasing significantly performance, In this paper, we discuss the suitable configuration strategies for caching dynamic content by our experimental results. Considering the system itself can provide support for caching static Web page, such as computer memory cache and disk＇s own cache, we adopt a special pattern that only caches dynamic Web page in some experiments to enlarge cache space. The paper is introduced three different replacement algorithms in our cache proxy module to test the practical effects of caching dynamic pages under different conditions. The paper is chiefly analyzed the influences of generated time and accessed frequency on caching dynamic Web pages. The paper is also provided the detailed experiment results and main conclusions in the paper.

关键词： web servers dynamic content caching configuration management replacement algorithm

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