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作者： John Ernest Lawson Naval Postgraduate School

学位级别：硕士

This thesis describes the need for including design for testability in a VLSI chip design and provides information on implementing a DFT strategy using the GENESIL Silicon Compiler. Two structured techniques of design for testability, Scan Design and Built-in Self Test, are discussed. Also, the methodology used to implement the residue code with GENESIL for testing the multiply-add module of a second-order Infinite Impulse Response notch filter is presented. The cost, in terms of increased hardware and decreased performance, associated with implementing the residue code is examined by comparing modulo-3 and modulo-15 checking algorithms.

关键词： design for testability scan design built-in self-test residue code notch filter silicon compiler

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On the residue codes of extremal Type II Z₄-codes of lengths 32 and 40

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DISCRETE MATHEMATICS 2011年第20期311卷 2148-2157页

作者： Harada, Masaaki Yamagata Univ Dept Math Sci Yamagata 9908560 Japan Japan Sci & Technol Agcy PRESTO Kawaguchi Saitama 3320012 Japan

In this paper, we determine the dimensions of the residue codes of extremal Type II Z(4)-codes of of lengths 32 and 40. We demonstrate that every binary doubly even self-dual code of length 32 can be realized as the residue code of some extremal Type II Z(4)-code. It is also shown that there is a unique extremal Type II Z(4)-code of length 32 whose residue code has the smallest dimension 6 up to equivalence. As a consequence, many new extremal Type II Z(4)-codes of lengths 32 and 40 are constructed. (C) 2011 Elsevier B.V. All rights reserved.

关键词： Extremal Type II Z(4)-code residue code Binary doubly even code

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Generating idempotents of quartic residue codes over the field F₄

Generating idempotents of quartic residue codes over the fie...

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International Forum on Computer and Information Technology (IFCIT)

作者： Dong, Xuedong Dalian Univ Coll Informat Engn Dalian 116622 Peoples R China

ISBN: (纸本)9783038350194

The generating polynomials of higher power residue codes over finite fields are difficult to construct. This paper gives explicit expressions of generating idempotents of quartic residue codes over the field F-4. The result will enable one to construct the generating polynomials of quartic residue codes over the field F-4 by computing the greatest common divisors of these generating idempotents and the polynomial x(n) - 1 with computer software such as Matlab and Maple.

关键词： Generating idempotent residue code Cyclic code

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DESIGN OF A RELIABLE AND SELF-TESTING VLSI DATAPATH USING residue CODING TECHNIQUES

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IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES 1986年第3期133卷 169-179页

作者： SAYERS, IL KINNIMENT, DJ CHESTER, EG Department of Electrical & Electronic Engineering University of Newcastle upon Tyne Newcastle upon Tyne UK

The testing of VLSI circuits is becoming progressively more difficult as device densities increase. This has brought about several proposals for designing VLSI circuits with testability built in. A method is presented in the paper for the design of easily testable VLSI circuits with a view to producing fault tolerant systems. A microprocessor datapath is used to illustrate the technique. The method used for checking the VLSI devices is an error detecting code, in this case a residue code. residue codes offer several advantages over linear block codes for providing testability in a wide range of VLSI circuits. A detailed evaluation of the increase in chip area required to produce a self testing chip is also given in the paper.

关键词： VLSI datapath self testing chip testable VLSI circuits circuit theory fault tolerant systems error detecting code VLSI circuits VLSI Semiconductor integrated circuits residue code residue coding techniques Logic design methods integrated circuit testing inbuilt testability linear block codes device densities fault tolerant computing microprocessor datapath

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An operation-centered approach to fault detection in symmetric cryptography ciphers

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IEEE TRANSACTIONS ON COMPUTERS 2007年第5期56卷 635-649页

作者： Breveglieri, Luca Koren, Israel Maistri, Paolo Politecn Milan Dept Elect & Informat Technol I-20133 Milan Italy Univ Massachusetts Dept Elect & Comp Engn Amherst MA 01003 USA TIMA Lab Grenoble France

One of the most effective ways of attacking a cryptographic device is by deliberate fault injection during computation, which allows retrieving the secret key with a small number of attempts. Several attacks on symmetric and public-key cryptosystems have been described in the literature and some dedicated error-detection techniques have been proposed to foil them. The proposed techniques are ad hoc ones and exploit specific properties of the cryptographic algorithms. In this paper, we propose a general framework for error detection in symmetric ciphers based on an operation-centered approach. We first enumerate the arithmetic and logic operations included in the cipher and analyze the efficacy and hardware complexity of several error-detecting codes for each such operation. We then recommend an error-detecting code for the cipher as a whole based on the operations it employs. We also deal with the trade-off between the frequency of checking for errors and the error coverage. We demonstrate our framework on a representative group of 11 symmetric ciphers. Our conclusions are supported by both analytical proofs and extensive simulation experiments.

关键词： cryptography symmetric cipher error-detecting code parity code residue code fault attacks fault detection

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New extremal Type II ℤ4-codes of length 64

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APPLICABLE ALGEBRA IN ENGINEERING COMMUNICATION AND COMPUTING 2024年 1-14页

作者： Martinovic, Sara Ban Rukavina, Sanja Univ Rijeka Fac Math Rijeka 51000 Croatia

Type II & Zopf;(4)-codes are a class of self-dual & Zopf;(4)-codes with Euclidean weights divisible by eight. A Type II & Zopf;(4)-code of length n is extremal if its minimum Euclidean weight is equal to 8... 详细信息

Type II & Zopf;(4)-codes are a class of self-dual & Zopf;(4)-codes with Euclidean weights divisible by eight. A Type II & Zopf;(4)-code of length n is extremal if its minimum Euclidean weight is equal to 8|n/24| + 8. A small number of such codes is known for lengths greater than or equal to 48. Based on the doubling method, in this paper we develop a method to construct new extremal Type II & Zopf;(4)-codes starting from a free extremal Type II & Zopf;(4)-code of length 48, 56 or 64. Using this method, we construct extremal Type II & Zopf;(4)-codes of length 64 and type 4(31)2(2) . Extremal Type II & Zopf;(4)-codes of length 64 of this type were not known before. Moreover, the residue codes of the con-structed extremal & Zopf;(4)-codes are best known [64, 31] binary codes and the supports of the minimum weight codewords of the residue code and the torsion code of one of these codes yields self-orthogonal 1-design.

关键词： residue code Doubling method Type II & Zopf (4)-code Extremal & Zopf (4)-code residue code Doubling method

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Bounds on relative generalised Hamming weight

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IET COMMUNICATIONS 2020年第11期14卷 1794-1804页

作者： Zhuang, Zhuojun Zhang, Keke Jing, Zhen Dai, Bin Huang, Jia Chinese Acad Sci Innovat Acad Microsatellites 99 Haike Rd Shanghai 201203 Peoples R China Southwest Jiaotong Univ Sch Informat Sci & Technol 111First SectNorth Second Ring Rd Chengdu 610031 Sichuan Peoples R China

The rth relative generalised Hamming weight (RGHW) of an [n, k] linear code C and an [n, k(1)] subcode C-1, a generalisation of generalised Hamming weight (GHW), characterises code performances of wiretap channel of type II, secure network coding, linear ramp secret sharing scheme, trellis complexity etc. In this study, the authors investigate non-asymptotic and asymptotic bounds on RGHW. In the non-asymptotic setting, they present a new proof of the Griesmer bound on RGHW by residue code and introduce the new concept of relative chain condition. They show that code pairs meeting the Griesmer, Singleton, and weak Plotkin bounds satisfy this condition. The notion of relative chain condition and these results provide a new perspective on researches including evaluating trellis complexity and determining the weight hierarchy of code pairs etc. In the asymptotic setting, they improve previous work by introducing two new metrics, respectively, for the cases r is fixed and r is proportionally increasing with n. They show the asymptotic Singleton, Plotkin, and Gilbert-Varshamov bounds on the first metric and determine the value of the second metric, which is helpful for characterising the optimal asymptotic performances of applications and constructing the optimal coding schemes.

关键词： Hamming codes network coding linear codes channel coding trellis codes Gilbert-Varshamov bounds optimal coding schemes relative generalised Hamming weight RGHW linear code secure network coding linear ramp secret sharing scheme trellis complexity asymptotic bounds nonasymptotic setting residue code relative chain condition weight hierarchy weak Plotkin bounds Griesmer bounds asymptotic Singleton bound setting

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Design of the coarse-grained reconfigurable architecture DART with on-line error detection

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MICROPROCESSORS AND MICROSYSTEMS 2014年第2期38卷 124-136页

作者： Jafri, S. M. A. H. Piestrak, S. J. Sentieys, O. Pillement, S. Royal Inst Technol KTH Elect Syst Lab SE-10044 Stockholm Sweden Univ Lorraine UMR CNRS 7198 Inst Jean Lamour F-54506 Vandoeuvre Les Nancy France Univ Rennes 1 CAIRN Res Team IRISA INRIA F-22300 Lannion France Univ Nantes Ecole Polytech Dept Elect & Technol Numer F-44306 Nantes France

This paper presents the implementation of the coarse-grained reconfigurable architecture (CGRA) DART with on-line error detection intended for increasing fault-tolerance. Most parts of the data paths and of the local memory of DART are protected using residue code modulo 3, whereas only the logic unit is protected using duplication with comparison. These low-cost hardware techniques would allow to tolerate temporary faults (including so called soft errors caused by radiation), provided that some technique based on re-execution of the last operation is used. Synthesis results obtained for a 90 nm CMOS technology have confirmed significant hardware and power consumption savings of the proposed approach over commonly used duplication with comparison. Introducing one extra pipeline stage in the self-checking version of the basic arithmetic blocks has allowed to significantly reduce the delay overhead compared to our previous design. (C) 2013 Elsevier B.V. All rights reserved.

关键词： Coarse-grained reconfigurable architecture (CGRA) Fault-tolerant system Reconfigurable system On-line error detection Self-checking circuit residue code Arithmetic code Temporary faults

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Generating Idempotents of Sixth residue codes over the Binary Field

Generating Idempotents of Sixth Residue Codes over the Binar...

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2017 2nd International Conference on Computer, Network Security and Communication Engineering(CNSCE2017)

作者： Xue-dong DONG Yan ZHANG College of Information Engineering Dalian University School of Mathematics Liaoning Normal University

Higher power residue codes over finite fields are generated by factors of the polynomial x~n-1. Unfortunately, to decompose the polynomial x~n-1 over finite fields is difficult. Generating idempotents can also generate higher power residue codes. Thus it is important to get generating idempotents of cyclic codes. We find precise expressions of generating idempotents of some sixth residue codes of length over the binary field, where p is a prime such that p ≡1（ mod 24）.

关键词： Generating idempotent residue code Cyclic code

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A high-level synthesis based dual-module redundancy with multi-residue detection(DMR-MRD)fault-tolerant method for on-board processing satellite communication systems

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High Technology Letters 2014年第3期20卷 245-252页

作者：杨文慧 Chen Xiang Wang Yu Zhao Ming Wang Jing Communication Engineering of Xiamen University Aerosapce Center Tsinghua University Department of Electronic Engineering Tsinghua University Wireless and Mobile Communication Technology R&D Center Tsinghua University

On board processing(OBP) satellite systems have obtained more and more attentions in recent years because of their high efficiency and ***,the OBP transponders are very sensitive to the high energy particles in the space radiation *** event upset(SEU)is one of the major radiation effects,which influences the satellite reliability *** modular redundancy(TMR) is a classic and efficient method to mask ***,TMR uses three identical modules and a comparison logic,the circuit size becomes unacceptable,especially in the resource limited environments such as OBP *** that,a new SEU-tolerant method based on residue code and high-level synthesis(HLS) is proposed,and the new method is applied to FIR filters,which are typical structures in the OBP *** simulation results show that,for an applicable HLS scheduling scheme,area reduction can be reduced by 48.26%compared to TMR,while fault missing rate is 0.15%.

关键词： single event upset (SEU) residue code triple modular redundancy (TMR) high-level synthesis (HLS) fault missing rate

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