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IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems

作者： Mojtaba Valinataj Pasi Liljeberg Juha Plosila Babol University of Technology University of Turku

ISBN: (纸本)9781467361354

The reliability is a vital aspect in the design of Network-on-Chip (NoC) based systems because a fault in communication medium may cause an overall system failure. On the other hand, performance degradation is an inescapable consequence of fault-tolerant architectures. In this paper, we propose a fault-tolerant NoC architecture that attains higher performance by using low cost agents in a hierarchical manner. These agents which are distributed all over the network, collect, process, and distribute different fault information. Moreover, we propose an enhanced fault-tolerant and congestion-aware routing method that exploits the classified fault information related to the permanent faults that might occur inside the links, network interfaces and different parts of the routers. The experimental results reveal that the proposed NoC architecture imposes small area and power overheads.

关键词： Network-on-chip Fault-tolerance Permanent fault routing algorithm Reconfiguration Congestion Fault tolerance permanent fault network-on-chip routing algorithms Reconfiguration misinformation system failures ARCHITECTURE Communications Media

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Power Analysis with Variable Traffic Loads for Next Generation Interconnection Networks

Power Analysis with Variable Traffic Loads for Next Generati...

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IEEE International Conference on High Performance Computing and Communications

作者： Faiz Al Faisal M.M. Hafizur Rahman Yasushi Inoguchi Sch. of Inf. Sci. JAIST Ishikawa Japan Dept. of Comput. Sci. IIUM Kuala Lumpur Malaysia Res. Center for Adv. Com. Infr. JAIST Ishikawa Japan

ISBN: (纸本)9781509042982

Power consumption is the most important factor for the consideration of next generation supercomputers. In addition, the requirement of power usages can be even scaled up to more than 300MW (which is nearly equal to the one nuclear power plant) with the conventional networks. On the other hand, hierarchical interconnection networks can be a possible solution to those issues. 3D-TTN is a hierarchical interconnection network where lowest level is configured as the 3Dtorus network, following the 2Dtorus network at the higher-level networks. The main focus for this paper is the power analysis with variable traffic load along with the fault tolerance, cost, packing density and message traffic density of 3D-TTN comparing against various other networks. In our early research, 3D-TTN has achieved near about 21% better diameter performance, 12% better average distance performance and eventually required about 32.48% less router power usage at the lowest level than the 5Dtorus network for 1% traffic load. This paper shows the power comparison with the router and link power rather than considering the router power only. Our analysis shows that 3D-TTN will require about 39.96% less router and link power than the 5Dtorus network for 10% traffic. With 30% traffic load, 3D-TTN will require about 38.42% less power than the 5Dtorus network for the on-chip network. Even considering some topological parameters, 3D-TTN could also achieve some desirable performance by comparing other networks.

关键词： 3D-TTN topological analysis message traffic density packing density fault tolerance routing algorithm estimation of power consumption

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Image based Experiment Scene Builder for Virtual Educational Experiments

Image based Experiment Scene Builder for Virtual Educational...

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第十一届中国虚拟现实大会(ICVRV2011)

作者： Changjian Chi Xiaowu Chen Ziqiang Yang Guodong Jia State Key Laboratory of Virtual Reality Technology and Systems School of Computer Science and Engineering Beihang University Beijing China

Realism and simplicity of virtual experiment scene building can influence the usage of virtual educational experiment applications. This paper proposes an image based method of experiment scene building for Virtual Educational Experiments. Firstly, virtual educational experiment components are extracted from images of experiment instrument by using the interactive method of object extraction. Then, the corresponding logical model descriptions are attached to the extracted components. Finally, the components required in a specific experiment are inserted into the selected virtual experiment scene and are connected interactively. A routing algorithm based on equivalent connection line is designed to make the generated line connections between components clear and legible. A virtual experiment scene building system, named VE Scene builder, has been implemented and widely used. The feedbacks demonstrated that our system can rapidly generate realistic and legible virtual experiment scene.

关键词： virtual educational experiment image based virtual scene building routing algorithm

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A Double-Layer Sparse Honeycomb Topology for NoC

A Double-Layer Sparse Honeycomb Topology for NoC

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International Conference on Computer Science and Network Technology

作者： Rong Gao Feiyang Liu Huaxi Gu Xisong Fu Shenzhen CU-Xidian Joint Center Xidian Univ. Xi'an China

ISBN: (纸本)9781479905607

Network-on-chip (NoC) is emerging as an effective architecture which address the shortcomings of traditional bus-based System-on-chip (SoC). Since its better properties, such as the lower power consumption, smaller size and higher scalability, mesh is often regarded as an effective topology for NoC design. In this paper, we propose a double-layer sparse honeycomb topology as a terrific design option gaining advantages of degree, diameter, and network cost which is vital to network performance. As a result of the fact that 3D IC has developed as a perspective technique for network topology, we transform the sparse honeycomb topology into rectangular brick shape that it is feasible to be implemented on the chip, and double the planar sparse honeycomb structure to obtain this advantageous 3D topology. Based on the addressed topology, a brief routing algorithm which is easy and improved from the dimension order routing algorithm is carried out. The 4×4 router for the new topology has been implemented and simulated. Thus, the degree of routers is reduced and the utilization is increased.

关键词： network routing network topology network-on-chip three-dimensional integrated circuits 3D IC NoC double-layer sparse honeycomb topology rectangular brick shape routing algorithm Computer architecture Conferences Network topology Ports (Computers) routing Three-dimensional displays Topology Network-on-Chip honeycomb layout router network-on-chip Network topology routing algorithms Network routing topology Honeycombs three-dimensional displays three-dimensional integrated circuits Computer Architecture NOCT gene Routers layouts

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Novel hierarchical interconnection networks for high-performance multicomputer systems

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JOURNAL OF INFORMATION SCIENCE AND ENGINEERING 2004年第6期20卷 1213-1229页

作者： Jan, GE Hwang, YS Lin, MB Liang, D Natl Taipei Univ Dept Comp Sci San Shia 237 Taiwan Natl Taiwan Ocean Univ Dept Comp Sci Chilung 202 Taiwan Natl Taiwan Univ Sci & Technol Dept Elect Engn Taipei 106 Taiwan

This paper proposes several novel hierarchical interconnection networks based on Heawood graphs, namely, folded Heawood networks, root-folded Heawood networks, recursively expanded Heawood networks, and flooded Heawood networks. Like hypercubes and networks extended from Petersen networks, these hierarchical Heawood networks have the following properties: regular topology, high scalability, and small diameter. Due to these important properties, these hierarchical Heawood networks seem to have potential as alternatives for future interconnection structures of multicomputer systems. Furthermore, this paper will demonstrate that the routing and broadcasting algorithms for these proposed networks are as elegant as the algorithms for hypercubes and Petersen-based networks.

关键词： broadcasting algorithm routing algorithm Heawood graph Heawood networks folded Heawood networks root-folded Heawood networks recursively expanded Heawood networks flooded Heawood networks

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GMCAST: A novel multicast algorithm of three-layer graphite structure in wireless data center network 2020

GMCAST: A novel multicast algorithm of three-layer graphite ...

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Proceedings of the 2020 International Conference on Cyberspace Innovation of Advanced Technologies

作者： Yingbo Wang Jun Li Hui Li School of Computer and Information Engineering Henan University Kaifeng Henan China Office of Information Management Henan University Kaifeng Henan China School of Henan University Minsheng College Kaifeng Henan China

ISBN: (纸本)9781450387828

In the research of data center network structure, routing algorithm is one of the important research fields, it is mainly to find a suitable path to transfer data information from the source node to the destination node. In this paper, multicast routing algorithm is designed for three layers of graphite structure with optimal performance. Graphite structure will be closer to practical application due to its own advantages. But the author did not design its routing algorithm. In recent years, group communication is becoming more popular. Multicast is becoming more important in group communication in current data center network. This paper introduces the construction of the three-layer graphite structure and designs the multicast routing algorithm of the three-layer graphite structure.

关键词： Wireless data center network routing algorithm Graphite structure

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A User-Controllable Multi-Layer Secure algorithm for MANET

A User-Controllable Multi-Layer Secure Algorithm for MANET

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International Wireless Communications and Mobile Computing Conference

作者： Paul Loh Ruen Chze Wayne Kan Wai Yan Kan Siew Leong Communications & Networks Group School of Engineering (Electronics) Nanyang Polytechnic Singapore

ISBN: (纸本)9781457713781

This paper introduces a User-Controllable Multi- Layer Secure algorithm (UMSA) to authenticate the MANET nodes before joining an existing MANET or formation of a new MANET by using the information from the user, the application layer, the network layer and the data-link layer. Currently, the authentication and the routing of the MANET nodes are two distinct processes. The proposed UMSA aims to embed the security information into the routing algorithm, thus combining the authentication and routing processes without incurring significant overheads. The MANET nodes are only allowed to form a MANET if the nodes are identified with a unique User- Controllable Identification, running users' pre-agreed application(s), and are in the list of permitted nodes, thus saving resources in the nodes by maintaining a smaller routing information. The experimental results show that the UMSA enhances the security of the MANET without negatively impacting the performance of the routing algorithm.

关键词： multi-layer authenticated mobile ad-hoc network MANET routing algorithm

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AF-CHORD: AN IMPROVED CHORD MODEL BASED ADJUSTED FINGER TABLE

AF-CHORD: AN IMPROVED CHORD MODEL BASED ADJUSTED FINGER TABL...

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2011 4th IEEE International Conference on Broadband Network & Multimedia Technology(第四届IEEE宽带网络与多媒体国际会议 4th IEEE IC-BNMT2011)

作者： Bai Wang Gengyu Wei Shidong Zhang Yuan Zhou School of Computer Science and Technology Beijing University of Posts and Telecommunications Beijin National Computer network Emergency Response Technical Team/Coordination Center of China Beijing C

This paper proposed an improved Chord model called AF-Chord, which is based on the adjusted constructor for Finger Table, and give out its routing algorithm. While constructing the Finger Table, we have considered the using of the redundancy table entries, and provide a improved routing algorithm. Through simulation experiment, we can prove that in the premise of a constant Finger Table capacity, the average length of logical routing path while seeking for resourses and the ability of load ba lancing have obviously been improved.

关键词： P2P Chord Model Finger Table routing algorithm routing Paths Load Balancing

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Distributed Internet Telephony system using a novel P2P architecture

Distributed Internet Telephony system using a novel P2P arch...

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2nd IEEE International Conference on Wireless Communications, Networking and Mobile Computing (WiCOM 2006)

作者： Dai Bin Wang Furong Liu Jian Huazhong Univ Sci & Technol Commun Software & Switch Technol Inst Wuhan Peoples R China

ISBN: (纸本)9781424405169

Recently years, research on Internet Telephony technology based on unstructured or structured peer-to-peer (P2P) networks has been developed rapidly. In such systems, the routing efficiency and their scalability are challenging two problems. The structured networks have rigorous restriction to search condition, and rely on rigorous network topology. The unstructured networks avoid the limitations of centralized systems but their search algorithms are usually based on simple flooding schemes, showing server inefficiencies. In order to address these major limitations, this paper considers the characters of users in Internet Telephony systems adequately, presents a novel P2P overlay network based on unstructured P2P networks, called Self-Organizing Multi-Character Overlay (SOMCO), which adopts small-world network to construct the topology, and presents the corresponding routing algorithm for the system. In our simulation, compared with existing P2P Internet Telephony system, SOMCO is much better on the routing efficiency and network scalability.

关键词： P2P VoIP small world routing algorithm

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A CAM‐based hardware implementation of the improved line‐search algorithm

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Electronics and Communications in Japan (Part III: Fundamental Electronic Science) 1993年第7期76卷 63-76页

作者： Kubota, Kazuto Sato, Masao Ohtsuki, Tatsuo Suzuki, Kei School of Science and Engineering Waseda University Tokyo 169 Japan Central Research Laboratory Hitachi Ltd. Kokubunji 185 Japan

In the routing process in VLSI and PCB, the “gridless router” has been considered where the routing is executed without using a grid. The improved line search algorithm is one of the gridless routers where the linesearch algorithm is extended so that the route search procedure is executed on a linear memory space in a polynomial time. The search of the route with the minimum bends is ensured. However, the algorithm has a problem in that the route is obtained by iterating the search of the two‐dimensional figures and the computational complexity of O(n log² n) at the minimum and O(n²) in the worst case is required for the layout area composed of n vertices. This paper notes that the complexity of solving the two‐dimensional figure search problem can be suppressed by using the associative memory and presents an algorithm for the improved line search using the associative memory where the time and space complexity is O(n). The proposed algorithm is implemented on the associative processor and the result is compared to the result of implementation on the general‐purpose computer. Copyright © 1993 Wiley Periodicals, Inc., A Wiley Company

关键词： Content addressable memory hardware engine routing algorithm VLSI layout

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