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A run-time optimization approach for reducing data movements using locality-aware searching

JOURNAL OF SUPERCOMPUTING 2014年第2期69卷 864-886页

作者： Li, Liang Wang, Endong Zhang, Xingjun Yan, Kang Ju, Tao Dong, Xiaoshe Xi An Jiao Tong Univ Xian 710049 Peoples R China State Key Lab High End Server & Storage Technol Jinan Peoples R China

The CPU-GPU communication bottleneck limits the performance improvement of GPU applications in heterogeneous GPGPU systems and usually is handled by data reuse optimization. This paper analyzes data reuse through DAG abstraction and obtains rules showing that the run-time data reuse optimization can effectively relieve the bottleneck. Based on the rules, this paper proposes a run-time optimization framework for data reuse, called R-Tracker. The R-Tracker uses locality-aware searching approach to handle reuses. It can not only low costly implement the data reuse optimization but also effectively implement the searching, the data transfers, and the GPU computation concurrently. R-Tracker relaxes the constraints that are required in compiler-based approaches and thus achieves better reuse effect. The experimental results show that R-Tracker improves the performance by 1.77-16.42 % over compiler-based approach OpenMPC and 1.40-8.39 % over CGCM in single-node execution, and 48.78-60 % over CGCM in multi-node execution.

关键词： CPU-GPU run-time optimization Dynamic searching Data reuse

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Robust Practical Binary optimization at run-time using LLVM 6

Robust Practical Binary Optimization at Run-time using LLVM

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IEEE/ACM 6th Workshop on the LLVM Compiler Infrastructure in HPC / Workshop on Hierarchical Parallelism for Exascale Computing (LLVM-HPC and HiPar)

作者： Engelke, Alexis Schulz, Martin Tech Univ Munich Munich Germany

ISBN: (纸本)9780738110424

In High Performance Computing (HPC) the performance of applications is paramount, which is has led to a wide body of work on optimizing compilers. However, compilers alone are naturally limited in their potential, as they cannot exploit run-time information to specialize generated code. For this reason, run-time components to perform such specializations are gaining traction. In particular, application or use-case driven specializations have a high potential for optimizations, as they can benefit from explicit guidance from the application or the user, which allows for targeted changes incorporating specific knowledge. Because full compilers and sources are usually unavailable during computation, specializations have to be done at machine code level. However, existing libraries for binary specialization face structural limitations of separating optimization and code generation, in addition to numerous implementation gaps. In this paper, we describe BinOpt, a novel and robust library for performing application-driven binary optimization and specialization using LLVM. A machine code function is lifted directly to LLVM-IR, optimized in LLVM while making use of application-specified information, used to generate a new specialization for a function, and integrated back to the original code. We apply this technique to existing optimized code and show that significant performance improvements can be observed with only a small optimization time overhead.

关键词： High Performance Computing Dynamic Code Generation run-time optimization Binary Translation LLVM

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Regenerative Breaking: Optimal Energy Recycling for Energy Minimization in Duty-Cycled Domains

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2022年第1期58卷 68-77页

作者： Huang, Chi-Hsiang Mandal, Arindam Pena-Colaiocco, Diego Da Silva, Edevaldo Pereira Sathe, Visvesh S. Univ Washington Dept Elect & Comp Engn Seattle WA 98195 USA NXP Semicond Austin TX 78735 USA Georgia Inst Technol Dept Elect & Comp Engn Atlanta GA 30332 USA

system on chip (SoC) domains in wearable and Internet-of-Things (IoT) applications are frequently duty-cycled, placed in a power-gated (Sleep) mode, and woken up for brief periods to perform tasks (Active mode). Duty cycling reduces steady-state leakage energy loss, but the significant quantity of energy stored in the domain decoupling capacitor (C-O) at the onset of Sleep mode is discharged through domain leakage. This energy overhead significantly degrades overall system efficiency. This article presents an architecture that efficiently reverses power flow in a buck converter at the onset of Sleep to recycle the stored energy stored in C-O before Sleep, thus minimizing transient Sleep leakage losses (E-loss). A fully digital run-time E-loss optimizer is presented to achieve optimal recycling and demonstrated in a voltage domain consisting of a duty-cycled, buck-regulated ARM M0 processor. Measurements indicate that 59.4% E(loss )reduction is achieved with 3.2-ms Sleep duration. These savings translate to total system energy savings of 56.6% for a duty-cycled processor executing 5k cycles during the Active operation.

关键词： DC-DC converter energy-autonomous integrated systems Internet of Things (IoT) power delivery run-time optimization wearable electronics

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Smart resource allocation of concurrent execution of parallel applications

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CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2023年第17期35卷

作者： da Silva, Vinicius S. Nogueira, Angelo G. D. de Lima, Everton Camargo Rocha, Hiago M. G. de A. Serpa, Matheus S. Luizelli, Marcelo C. Rossi, Fabio D. Navaux, Philippe O. A. Beck, Antonio Carlos S. Lorenzon, Arthur Francisco Fed Univ Pampa Optimizat Syst Lab Campus Alegrete Alegrete Brazil Univ Fed Rio Grande do Sul Inst Informat Porto Alegre RS Brazil Fed Inst Farroupilha Optimizat Syst Lab Alegrete Brazil

Thread-level parallelism (TLP) has been widely exploited to optimize computational resource usage in high-performance systems. However, as many applications do not scale as the number of threads increase, resources will be wasted when the application executes with the maximum possible number of threads (i.e., the default execution) rather than fewer threads (thread throttling) that may use the resources more efficiently. Hence, instead of executing only one application with as many threads as possible, one can run more applications simultaneously by applying thread throttling to each one. The primary outcome of this strategy is a significant reduction in the total execution time and energy consumption when the system needs to execute a list of applications. Given that, we propose a smart resource allocation (SRA) for concurrent parallel application execution. It automatically finds the ideal degree of TLP for each application and guides the simultaneous parallel applications execution. When running 25 well-known benchmarks on three multicore systems and comparing SRA to state-of-the-art strategies (e.g., Batch, Equal policy, and Scalability), SRA improves the EDP by 87.4% over the Batch strategy;75.5% over the Equal policy;and 38.8% over the scalability strategy.

关键词： energy-delay product parallel computing run-time optimization

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An FPU design template to optimize the accuracy-efficiency-area trade-off

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SUSTAINABLE COMPUTING-INFORMATICS & SYSTEMS 2021年第PartA期29卷

作者： Zoni, Davide Galimberti, Andrea Fornaciari, William DEIB Politecn Milano I-20133 Milan Italy

Modern embedded systems are in charge of an increasing number of tasks that extensively employ floating-point (FP) computations. The ever-increasing efficiency requirement, coupled with the additional computational effort to perform FP computations, motivates several microarchitectural optimizations of the FPU. This manuscript presents a novel modular FPU microarchitecture, which targets modern embedded systems and considers heterogeneous workloads including both best-effort and accuracy-sensitive applications. The design optimizes the EDP-accuracy-area figure of merit by allowing, at design-time, to independently configure the precision of each FP operation, while the FP dynamic range is kept common to the entire FPU to deliver a simpler micro architecture. To ensure the correct execution of accuracy-sensitive applications, a novel compiler pass allows to substitute each FP operation for which a low-precision hardware support is offered with the corresponding soft float function call. The assessment considers seven FPU variants encompassing three different state-of-the-art designs. The results on several representative use cases show that the binary32 FPU implementation offers an EDP gain of 15%, while, in case the FPU implements a mix of binary32 and bfloat16 operations, the EDP gain is 19%, the reduction in the resource utilization is 21% and the average accuracy loss is less than 2.5%. Moreover, the resource utilization of our FPU variants is aligned with the one of the FPU employing state-of-the-art, highly specialized FP hardware accelerators. Starting from the assessment, a set of guidelines is drawn to steer the design of the FP hardware support in modern embedded systems.

关键词： Floating Point Units (FPU) Accuracy-Cost-energy tradeoff run-time optimization

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Autotuning PostgreSQL: a blueprint for successful autotuning of real-world applications 18

Autotuning PostgreSQL: a blueprint for successful autotuning...

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Proceedings of the 40th International Conference on Software Engineering: Companion Proceeedings

作者： Thomas Karcher Mathias Landhäußer Karlsruhe Institute of Technology Karlsruhe thingsTHINKING GmbH Karlsruhe

ISBN: (纸本)9781450356633

Autotuning is a technique for optimizing the performance of sequential and parallel applications. We explore the problem of successfully applying on-line autotuning to real-world applications. We tune PostgreSQL, an open-source database server software, by optimizing tuning parameters that affect table scans. We evaluate the effects on the performance using the TPC-H benchmark and achieve speedups up to 3.9. A video subsuming the process is available at https://***/10.5445/DIVA/2018-192.

关键词： run-time optimization PostgreSQL parameter tuning heuristic search-based on-line autotuning database

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Adaptive, Efficient, Parallel Execution of Parallel Programs 14

Adaptive, Efficient, Parallel Execution of Parallel Programs

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35th ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI)

作者： Sridharan, Srinath Gupta, Gagan Sohi, Gurindar S. Univ Wisconsin Madison WI 53706 USA

ISBN: (纸本)9781450327848

Future multicore processors will be heterogeneous, be increasingly less reliable, and operate in dynamically changing operating conditions. Such environments will result in a constantly varying pool of hardware resources which can greatly complicate the task of efficiently exposing a program's parallelism onto these resources. Coupled with this uncertainty is the diverse set of efficiency metrics that users may desire. This paper proposes Varuna, a system that dynamically, continuously, rapidly and transparently adapts a program's parallelism to best match the instantaneous capabilities of the hardware resources while satisfying different efficiency metrics. Varuna is applicable to both multithreaded and task-based programs and can be seamlessly inserted between the program and the operating system without needing to change the source code of either. We demonstrate Varuna's effectiveness in diverse execution environments using unaltered C/C++ parallel programs from various benchmark suites. Regardless of the execution environment, Varuna always outperformed the state-of-the-art approaches for the efficiency metrics considered.

关键词： Design Experimentation Measurement Performance Autotuning parallel programming performance portability performance tuning run-time optimization

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A Survey and Taxonomy of On-Chip Monitoring of Multicore Systems-on-Chip

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ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 2013年第2期18卷 1-38页

作者： Kornaros, Georgios Pnevmatikatos, Dionisios Tech Univ Crete Dept Elect & Comp Engn Khania 73100 Greece

Billion transistor systems-on-chip increasingly require dynamic management of their hardware components and careful coordination of the tasks that they carry out. Diverse real-time monitoring functions assist towards this objective through the collection of important system metrics, such as throughput of processing elements, communication latency, or resource utilization for each application. The online evaluation of these metrics can result in localized or global decisions that attempt to improve aspects of system behavior, system performance, quality-of-service, power and thermal effects under nominal conditions. This work provides a comprehensive categorization of monitoring approaches used in multiprocessor SoCs. As adaptive systems are encountered in many disciplines, it is imperative to present the prominent research efforts in developing online monitoring methods. To this end we offer a taxonomy that groups strongly related techniques that designers increasingly use to produce more efficient and adaptive chips. The provided classification helps to understand and compare architectural mechanisms that can be used in systems, while one can envisage the innovations required to build real adaptive and intelligent systems-on-chip.

关键词： Design Performance Reliability Security On-chip monitoring dynamic management multicore network-on-chip adaptive SoC on-line debugging run-time optimization reconfiguration diagnosis fault tolerance security proactive SoC management

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Activity pre-scheduling for run-time optimization of grid workflows

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JOURNAL OF SYSTEMS ARCHITECTURE 2008年第9期54卷 883-892页

作者： Tretola, Giancarlo Zimeo, Eugenio Univ Sannio Res Ctr Software Technol I-82100 Benevento Italy

The capability to support resource sharing between different organizations and high-level performance are noteworthy features of grid computing. Applications require significant design effort and complex coordination of resources to define, deploy and execute components on heterogeneous and often unknown resources. A common trend today aims at diffusing workflow management techniques to reduce the complexity of grid systems through model-driven approaches that significantly simplify application design through the composition of distributed services often belonging to different organizations. With this approach, the adoption of efficient workflow enactors becomes a key aspect to improve efficiency through run-time optimizations, so reducing the burden for the developer, who is only responsible of defining the functional aspects of complex applications since he/she has only to identify the activities that characterize the application and the causal relationships among them. This paper focuses on performance improvements of grid workflows by presenting a new pattern for workflow design that ensures activity pre-scheduling at run-time through a technique that generates fine-grained concurrency with a couple of concepts: asynchronous invocation of services and continuation of execution. The technique is implemented in a workflow enactment service that dynamically optimizes process execution with a very limited effort for application developer. (C) 2008 Elsevier B.V. All rights reserved.

关键词： grid computing grid workflow run-time optimization asynchronous invocation

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Quantifying the Wave-Effect of Irregular LDPC codes based on Majority-Based Hard-Decoding

Quantifying the Wave-Effect of Irregular LDPC codes based on...

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4th International Conference on Signal Processing and Communication Systems (ICSPCS)/12th International Symposium on DSP and Communication Systems (DSPCS)/9th Workshop on the Internet, Telecommunications and Signal Processing (WTSP)

作者： Mahmood, Asad Ctr Adv Studies Engn Dept ECE Islamabad 44000 Pakistan

ISBN: (纸本)9781424479078

Irregular LDPC codes have shown to give performances closer to capacity than their regular counteparts. The intuitive reasoning backed by experimental evidence given by its founder (Luby et al.) was the presence of a wave-effect. It was shown that only with the presence of a carefully optimized irregularity degree profile, comes the better performance. Conventionally this irregularity profile is optimized employing asymptotic assumptions which studies have shown result in poor performance measures in finite-length codes. Also, the conventional techniques are computationally expensive which makes their use inappropriate in cases, e.g. multicarrier [1], where run-time optimization of the irregularity profile may be needed. This paper proposes a simplistic technique for precise quantification of the wave-effect phenomenon in irregular codes and hence can be used for run-time optimization of irregularity in finite length codes which may not be possible with classical methods.

关键词： finite-length codes intuitive reasoning irregular LDPC codes majority-based hard-decoding parity check codes run-time optimization wave-effect wave-effect

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