polar codes are one of the most favorable capacity-achieving codes owing to their simple structures and low decoding complexity. Successive cancellation list(scl) decoders with large list sizes achieve performances ve...
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polar codes are one of the most favorable capacity-achieving codes owing to their simple structures and low decoding complexity. Successive cancellation list(scl) decoders with large list sizes achieve performances very close to those of maximum-likelihood(ML) decoders. However, hardware cost is a severe problem because an scldecoder with list size L consists of L copies of a successive cancellation(SC)decoder. To address this issue, a stochastic scl(Sscl) polardecoder is proposed. Although stochastic computing can achieve a good hardware reduction compared with the deterministic one, its straightforward application to an scldecoder is not well-suited owing to the precision loss and severe latency. Therefore,a doubling probability approach and adaptive distributed sorting(DS) are introduced. A corresponding hardware architecture is also developed. Field programmable gate array(FPGA) results demonstrate that the proposed stochastic scl polar decoder can achieve a good performance and complexity tradeoff.
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