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Vectorizing programs with IF-statements for processors with simd extensions

JOURNAL OF SUPERCOMPUTING 2020年第6期76卷 4731-4746页

作者： Sun, Huihui Gorlatch, Sergei Zhao, Rongcai Univ Munster Munster Germany Natl Digital Switching Syst Engn & Technol Res Ct Zhengzhou Henan Peoples R China

Vectorization of programs is crucial for achieving high performance on modern processors with simd (Single Instruction Multiple Data) extensions. Programs with IF-statements suffer from control flow divergence that seriously complicates automatic vectorization. Therefore, contemporary compilers employ the IF-conversion approach to convert control flow to data flow, which relies on using predicated execution techniques (i.e., masked or select simd instructions). In this paper, we enhance the compiler's capabilities to generate efficiently vectorized code for processors without masked instructions. We improve the state of the art in program vectorization by developing a novel approach-IF-select transformation-which is applicable to arbitrarily nested IF-statements. We implement our approach in the open-source Open64 compiler and evaluate its performance on the SW26010 processor used in the Sunway TaihuLight supercomputer (currently #3 in the TOP500 list) that does not support masked instructions. We extend our vectorization approach by providing an additional LLVM optimization pass to reduce the amount of masked memory accesses on processors without masked instructions, e.g., IBM Power8 and ARMCortex-A8. Experimental results demonstrate the performance advantages of the suggested vectorization techniques.

关键词： Compiler optimization simd extensions IF-conversion Masked instructions Select instructions

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Refactoring Loops with Nested IFs for simd extensions Without Masked Instructions 24th

Refactoring Loops with Nested IFs for SIMD Extensions Withou...

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International European Conference on Parallel and Distributed Computing (Euro-Par)

作者： Sun, Huihui Gorlatch, Sergei Zhao, Rongcai Univ Munster Munster Germany Natl Digital Switching Syst Engn & Technol Res Ct Zhengzhou Peoples R China

ISBN: (纸本)9783030105495;9783030105488

Most CPUs in heterogeneous systems are now equipped with simd (Single Instruction Multiple Data) extensions that operate on short vectors in parallel to enable high performance. Refactoring programs for such systems relies on vectorization, i.e., transforming into a form with simd-instructions. We improve the state of the art in refactoring loops with nested IF-statements that are notoriously difficult to vectorize. For IF-statements whose conditions are independent of the loop variable, we improve the classical loop unswitching method, such that it can tackle nested IFs. For IF-statements whose conditions change with loop iterations, we develop a novel IF-select transformation method: (1) it can work with arbitrarily nested IFs, and (2) while previous methods rely on either masked instructions or hardware support for predicated execution, our method works for simd extensions without such operations (as found, e.g., in IBM Power8 and ARM Cortex-A8). Our experimental evaluation for the SPEC CPU2006 benchmark suite is conducted on an SW26010 processor used in the Sunway TaihuLight supercomputer (#2 in the TOP500 list);it demonstrates the performance advantages of our implemented approach over the vectorizer of the Open64 compiler.

关键词： simd extensions Nested IF-statements Loop vectorization Loop unswitching IF-select transformation

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A performance analysis of a mimetic finite difference scheme for acoustic wave propagation on GPU platforms

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CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2017年第4期29卷

作者： Otero, Beatriz Frances, Jorge Rodriguez, Robert Rojas, Otilio Solano, Freysimar Guevara-Jordan, Juan Univ Politecn Cataluna Dept Arquitectura Comp Barcelona Spain Dept Fis Ingn Sistemes & Teoria Senal E-03080 Alicante Spain Univ Alicante Inst Univ Fis Aplicada Ciencias & Tecnol E-03080 Alicante Spain Univ Politecn Cataluna Escola Tecn Super Engn Telecomunicacio Barcelona Barcelona Spain Cent Univ Venezuela Fac Ciencias Escuela Computac Caracas Venezuela Barcelona Supercomp Ctr Dept Comp Applicat Sci & Engn Barcelona Spain Cent Univ Venezuela Fac Ciencias Escuela Matemat Caracas Venezuela

Realistic applications of numerical modeling of acoustic wave dynamics usually demand high-performance computing because of the large size of study domains and demanding accuracy requirements on simulation results. Forward modeling of seismic motion on a given subsurface geological structure is by itself a good example of such applications, and when used as a component of seismic inversion tools or as a guide for the design of seismic surveys, its computational cost increases enormously. In the case of finite difference methods (or any other volumen-discretization scheme), memory and computing demands rise with grid refinement, which may be necessary to reduce errors on numerical wave patterns and better capture target physical devices. In this work, we present several implementations of a mimetic finite difference method for the simulation of acoustic wave propagation on highly dense staggered grids. These implementations evolve as different optimization strategies are employed starting from appropriate setting of compilation flags, code vectorization by using streaming simd extensions Advanced Vector extensions (AVX), CPU parallelization by exploiting the Open Multi-Processing framework to the final code parallelization on graphics processing unit platforms. We present and discuss the increasing processing speed up of this mimetic scheme achieved by the gradual implementation and testing of all these performance optimizations. In terms of simulation times, the performance of our graphics processing unit parallel implementations is consistently better than the best CPU version. Copyright (C) 2016 John Wiley & Sons, Ltd.

关键词： acoustic waves mimetic finite differences simd extensions GPU CUDA programming

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Outer-Loop Auto-Vectorization for simd Architectures Based on Open64 Compiler 17

Outer-Loop Auto-Vectorization for SIMD Architectures Based o...

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17th International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT)

作者： Wang Dong Zhao Rongcai Wang Qi Li Yingying PLA Informat Engn Univ Zhengzhou Peoples R China

ISBN: (纸本)9781509050819

simd (Single Instruction Multiple Data) extensions are acceleration components integrated in general processor, aiming at extracting instruction and data level parallelism of multimedia and scientific calculation programs. Currently, most of the automatic vectorization methods for simd architectures are based on innermost loops. Inner loop vectorization is the common approach for auto-vectorization. This method has been used for many years and its efficiency is widely accepted by people. In this paper, we put forward a better method than inner loop vectorization for some loop nests, which is outer loop vectorization. Outer loop vectorization method means vectorizing the outer loop directly. It can extract more data level parallelism and make the most use of the spatial locality to improve the program efficiency than the inner one which is more suitable for some loop nests. This paper presents the realization. In this paper, we first revisit the preliminary analysis of outer loop vectorization based on Open64 complier. And then, data type conversion and code generation is presented in detail. Finally, we propose two optimization methods, capable of boosting the performance of outer loop vectorization to achieve the acceleration of 20% on average, 50% at most.

关键词： simd extensions vectorization method outer loop vectorization data level parallelism

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Efficient construction of bounding volume hierarchies into a complete octree for ray tracing

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COMPUTER ANIMATION AND VIRTUAL WORLDS 2016年第3-4期27卷 358-368页

作者： Olivares, Ulises Rodriguez, Hector G. Garcia, Arturo Ramos, Felix F. Univ Nacl Autonoma Mexico Dept Computat Biol Lab Nacl Anal & Sintesis Ecol Escuela Nacl Estudios Super Unidad Morelia Morelia Michoacan Mexico IPN Ctr Invest & Estudios Avanzados Dept Elect Engn & Comp Sci Unidad Guadalajara Guadalajara Jalisco Mexico Intel Guadalajara Design Ctr Visual Parallel Comp Grp Guadalajara Jalisco Mexico

This paper proposes an efficient construction scheme for bounding volume hierarchies based on a complete tree. This construction offers up to 4x faster construction times than binned-surface area heuristic and offers competitive ray traversal performance. The construction is fully parallelized on x86 CPU architectures;it takes advantage of the eight-wide vector units and exploits the advance vector extensions available for current x86 CPU architectures. Additionally, this work presents a clustering algorithm for grouping primitives, which can be computed in linear time O(n). Furthermore, this construction uses the graphics processing unit to perform intensive operations efficiently. Copyright (C) 2016 JohnWiley & Sons, Ltd.

关键词： Ray tracing octree simd extensions binary partition dynamic scenes

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Efficient construction of bounding volume hierarchies into a complete octree for ray tracing

Efficient construction of bounding volume hierarchies into a...

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Computer Animation and Social Agents (CASA) Conference

关键词： Ray tracing octree simd extensions binary partition dynamic scenes

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Multi-GPU and multi-CPU accelerated FDTD scheme for vibroacoustic applications

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COMPUTER PHYSICS COMMUNICATIONS 2015年第1期191卷 43-51页

作者： Frances, J. Otero, B. Bleda, S. Gallego, S. Neipp, C. Marquez, A. Belendez, A. Univ Alicante Dpto Fis Ingn Sistemas & Teoria Senal E-03080 Alicante Spain Univ Alicante Inst Univ Fis Aplicada Las Ciencias & Tecnol E-03080 Alicante Spain Univ Politecn Cataluna Dept Arquitectura Comp Barcelona Spain

The Finite-Difference Time-Domain (FDTD) method is applied to the analysis of vibroacoustic problems and to study the propagation of longitudinal and transversal waves in a stratified media. The potential of the scheme and the relevance of each acceleration strategy for massively computations in FDTD are demonstrated in this work. In this paper, we propose two new specific implementations of the bidimensional scheme of the FDTD method using multi-CPU and multi-GPU, respectively. In the first implementation, an open source message passing interface (OMPI) has been included in order to massively exploit the resources of a biprocessor station with two Intel Xeon processors. Moreover, regarding CPU code version, the streaming simd extensions (SSE) and also the advanced vectorial extensions (AVX) have been included with shared memory approaches that take advantage of the multi-core platforms. On the other hand, the second implementation called the multi-GPU code version is based on Peer-to-Peer communications available in CUDA on two GPUs (NVIDIA GTX 670). Subsequently, this paper presents an accurate analysis of the influence of the different code versions including shared memory approaches, vector instructions and multi-processors (both CPU and GPU) and compares them in order to delimit the degree of improvement of using distributed solutions based on multi-CPU and multi-GPU. The performance of both approaches was analysed and it has been demonstrated that the addition of shared memory schemes to CPU computing improves substantially the performance of vector instructions enlarging the simulation sizes that use efficiently the cache memory of CPUs. In this case GPU computing is slightly twice times faster than the fine tuned CPU version in both cases one and two nodes. However, for massively computations explicit vector instructions do not worth it since the memory bandwidth is the limiting factor and the performance tends to be the same than the sequential version with

关键词： FDTD GPU computing OMPI simd extensions

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Performance Evaluation of Multi-Core Intel Xeon Processors on Basic Linear Algebra Subprograms

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PARALLEL PROCESSING LETTERS 2009年第1期19卷 159-174页

作者： Soliman, Mostafa I. South Valley Univ Aswan Fac Engn Elect Engn Dept Comp & Syst Sect Aswan 81542 Egypt

Multi-core technology is a natural next step in delivering the benefits of Moore's law to computing platforms. On multi-core processors, the performance of many applications would be improved by parallel processing threads of codes using multi-threading techniques. This paper evaluates the performance of the multi-core Intel Xeon processors on the widely used basic linear algebra subprograms (BLAS). On two dual-core Intel Xeon processors with Hyper-Threading technology, our results show that a performance of around 20 GFLOPS is achieved on Level-3 (matrix-matrix operations) BLAS using multi-threading, simd, matrix blocking, and loop unrolling techniques. However, on a small size of Level-2 (matrix-vector operations) and Level-1 (vector operations) BLAS, the use of multi-threading technique speeds down the execution because of the thread creation overheads. Thus the use of Intel simd instruction set is the way to improve the performance of single-threaded Level-2 (6 GFLOPS) and Level-1 BLAS (3 GFLOPS). When the problem size becomes large (cannot fit in L2 cache), the performance of the four Xeon cores is less than 2 and 1 GFLOPS on Level-2 and Level-1 BLAS, respectively, even though eight threads are executed in parallel on eight logical processors.

关键词： multi-core computation multi-threaded technique performance evaluation BLAS matrix blocking simd extensions

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On the suitability of simd extensions for neural network simulation

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MICROPROCESSORS AND MICROSYSTEMS 2003年第7期27卷 341-351页

作者： Strey, A Univ Ulm Dept Neural Informat Proc D-89069 Ulm Germany

Current microprocessors contain simd execution units (also called multimedia or vector extensions) that allow the data-parallel execution of operations on several subwords packed in 64-bit or 128-bit registers. They can accelerate not only typical multimedia applications but also many other algorithms based on vector and matrix operations. In this paper the results of a detailed experimental study about the suitability of such units for the fast simulation of neural networks are presented. It is shown that a speedup in the range from 2.0 to 8.6 compared to sequential implementations can be achieved. A performance counter analysis is provided to explain several effects by features of the processor architecture. (C) 2003 Elsevier Science B.V. All rights reserved.

关键词： microprocessors simd extensions data-parallel processing neural networks

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Performance comparison of simd implementations of the discrete wavelet transform

Performance comparison of SIMD implementations of the discre...

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16th IEEE International Conference on Application-Specific Systems, Architecture and Processors

作者： Shahbahrami, A Juurlink, B Vassiliadis, S Delft Univ Technol Fac Elect Engn Math & Comp Sci Comp Engn Lab NL-2600 AA Delft Netherlands

ISBN: (纸本)0769524079

This paper focuses on simd implementations of the 2D discrete wavelet transform (DWT). The transforms considered are Daubechies' real-to-real method of four coefficients (Daub-4) and the integer-to-integer (5, 3) lifting scheme. Daub-4 is implemented using SSE and the lifting scheme using MMX, and their performance is compared to C implementations on a Pentium 4 processor The MMX implementation of the lifting scheme is up to 4.0x faster than the corresponding C program for a 1-level 2D DWT while the SSE implementation of Daub-4 is up to 2.6x faster than the C version. It is shown that for some image sizes, the performance is significantly hampered by the so-called 64K aliasing problem, which occurs in the Pentium 4 when two data blocks are accessed that are a multiple of 64K apart. It is also shown that for the (5, 3) lifting scheme, a 12-bit word size is sufficient for a 5-level decomposition of the 2D DWT for images of up to 10 bits per pixel.

关键词： discrete wavelet transform lifting scheme simd extensions

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