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IEEE Workshop on Signal Processing Systems (SiPS 2009)

作者： Ahn, Jaewoo Chang, Hoseok Cho, Junho Sung, Wonyong Seoul Natl Univ Sch Elect Engn Seoul 151742 South Korea

ISBN: (纸本)9781424443345

Implementation of recursive equations using parallel computer architecture has long been of interest because the dependency problem makes it difficult to achieve significant speed-up. In this paper, efficient implementation of recursive filtering equations on partitioned data-path simd (Single Instruction Multiple Data) processors is studied. Especially, three parallel computation techniques, which are the block filtering, recursive doubling, and multi-block filtering methods, are implemented and their performances are compared using a Pentium CPU based system. The performance evaluation result of the multi-block processing method on a scalable simd processor is also presented.

关键词： parallel computation recursive filtering partitioned data-path simd processor

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Implementation of the AVS Video Decoder on a Heterogeneous Dual-Core simd processor

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IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 2011年第2期57卷 673-681页

作者： Koziri, Maria Zacharis, Dimitrios Katsavounidis, Ioannis Bellas, Nikos Univ Thessaly Dept Comp & Commun Engn Volos 38221 Greece

Multi-core Application Specific Instruction processors (ASIPs) are increasingly used in multimedia applications due to their high performance and programmability. Nonetheless, their efficient use requires extensive modifications to the initial code in order to exploit the features of the underlying architecture. In this paper, through the example of implementing Advance Video Coding (AVS) to a heterogeneous dual-core simd processor, we present a guide to developers who wish to perform task-level decomposition of any video decoder in a multi-core simd system. Through the process of mapping AVS video decoder to a dual-core simd processor we aim to explore the different forms of parallelism inherent in a video application and exploit to speed-up AVS decoding in order to achieve real time functionality. Simulation results showed that the extraction of parallelism at all levels of granularity, especially at the higher levels, can give a total speed-up of more than 195x compared to a software x86-based implementation, which enables real-time, 25fps decoding of D1 video(1).

关键词： AVS video decoder simd processor multi core processor

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Compiler-Based Performance Evaluation of an simd processor with a Multi-Bank Memory Unit

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JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2009年第2-3期56卷 249-260页

作者： Chang, Hoseok Cho, Junho Sung, Wonyong Seoul Natl Univ Sch Elect Engn Seoul South Korea

The single instruction multiple data (simd) architecture is very efficient for executing arithmetic intensive programs, but frequently suffers from data-alignment problems. The data-alignment problem not only induces extra time overhead but also hinders automatic vectorization of the simd compiler. In this paper, we compare three on-chip memory systems, which are single-bank, multi-bank, and multi-port, for the simd architecture to resolve the data-alignment problems. The single-bank memory is the simplest, but supports only the aligned accesses. The multi-bank memory requires a little higher complexity, but enables the unaligned accesses and the stride accesses with a bank-conflict limitation. The multi-port memory is capable of both the unaligned and stride accesses without any restriction, but needs quite much expensive hardware. We also developed a vectorizing compiler that can conduct dynamic memory allocation and simd code generation. The performances of the three memory systems with our simd compiler are evaluated using several digital signal processing kernels and the MPEG2 encoder. The experimental results show that the multi-bank memory can carry out MPEG2 encoding 5.8 times faster, whereas the single-bank memory only achieves 2.9 times speed-up when employed in a multimedia system with a 2-issue host processor and an 8-way simd coprocessor. The multi-port memory obviously shows the best performance, which is however an impractical improvement over the multi-bank memory when the hardware cost is considered.

关键词： simd processor On-chip memory Multi-bank memory Vectorizing compiler Data allocation

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An Implementation of a Spiking Neural Network Using Digital Spiking Silicon Neuron Model on a simd processor 26th

An Implementation of a Spiking Neural Network Using Digital ...

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26th International Conference on Artificial Neural Networks (ICANN)

作者： Hori, Sansei Zapata, Mireya Madrenas, Jordi Morie, Takashi Tamukoh, Hakaru Kyushu Inst Technol Grad Sch Life Sci & Syst Engn Kitakyushu Fukuoka Japan Univ Politecn Cataluna Dept Elect Engn Barcelona Spain

ISBN: (纸本)9783319686004;9783319685991

We implement a digital spiking silicon neuron (DSSN) [1] in a single instruction multiple data (simd) processor. The simd processor is a scalable, reconfigurable, and real-time spiking neural network emulator based on field programmable gate arrays [2]. We implement the DSSN model in the simd processor for the first time. The behavior of the membrane potential of one neuron based on the DSSN model is shown in Fig. 1. The operation results of the simd processor with 16-bit fixed-point operation are compared with software simulation results based on 64-bit floating-point operation. From the results, it is concluded that the simd processor successfully emulated the behavior of the membrane potential. In addition, a full-connection network consisting of 100 neurons is simulated in a software using fixed-point binary numbers to evaluate the bit width for the simd processor. In this experiment, the network stores two patterns selected from [1]. In the recall phase, the first pattern with noise is given to this network to recall the pattern. Experimental results show that the network with 16-bit fixed-point numbers, each of which includes a 12-bit fraction, a 3-bit integer, and a 1-bit sign, successfully recalled the input pattern as shown in Fig. 2. Here, M_u is a recall rate [1]. From this result, a large DSSN network simulation on the simd processor is promising. © Springer International Publishing AG 2017.

关键词： SNN DSSN simd processor FPGA

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A Scalable simd RISC-V based processor with Customized Vector Extensions for CRYSTALS-Kyber 22

A Scalable SIMD RISC-V based Processor with Customized Vecto...

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59th ACM/IEEE Design Automation Conference (DAC) - From Chips to Systems - Learn Today, Create Tomorrow

作者： Li, Huimin Mentens, Nele Picek, Stjepan Delft Univ Technol Delft Netherlands Leiden Univ Leiden Netherlands Katholieke Univ Leuven Leuven Belgium Radboud Univ Nijmegen Nijmegen Netherlands

ISBN: (纸本)9781450391429

This paper uses RISC-V vector extensions to speed up lattice-based operations in architectures based on HW/SW co-design. We analyze the structure of the number-theoretic transform (NTT), inverse NTT (INTT), and coefficient-wise multiplication (CWM) in CRYSTALS-Kyber, a lattice-based key encapsulation mechanism. We propose 12 vector extensions for CRYSTALS-Kyber multiplication and four for finite field operations in combination with two optimizations of the HW/SW interface. This results in a speed-up of 141.7, 168.7, and 245.5 times for NTT, INTT, and CWM, respectively, compared with the baseline implementation, and a speed-up of over four times compared with the state-of-the-art HW/SW co-design using RV32IMC.

关键词： Lattice-based Cryptography Polynomial Operation Vector Instruction simd processor RISC-V ISA Extension

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Software Programmable Data Allocation in Multi-Bank Memory of simd processors

Software Programmable Data Allocation in Multi-Bank Memory o...

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13th Euromicro Conference on Digital System Design on Architectures, Methods and Tools

作者： Wang, Jian Sohl, Joar Kraigher, Olof Liu, Dake Linkoping Univ Dept Elect Engn Linkoping Sweden

ISBN: (纸本)9780769541716

The host-simd style heterogeneous multi-processor architecture offers high computing performance and userfriendly programmability. It explores both task level parallelism and data level parallelism by the on-chip multiple simd coprocessors. For embedded DSP applications with predictable computing feature, this architecture can be further optimized for performance, implementation cost and power consumption. The optimization could be done by improving the simd processing efficiency and reducing redundant memory accesses and data shuffle operations. This paper introduces one effective approach by designing a software programmable multi-bank memory system for simd processors. Both the hardware architecture and software programming model are described in this paper, with an implementation example of the BLAS syrk routine. The proposed memory system offers high simd data access flexibility by using lookup table based address generators, and applying data permutations on both DMA controller interface and simd data access. The evaluation results show that the simd processor with this memory system can achieve high execution efficiency, with only 10% to 30% overhead. The proposed memory system also saves the implementation cost on simd local registers;in our system, each simd core has only 8 128-bit vector registers.

关键词： simd processor multi-bank memory conffict free memory access data allocation

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processor-based turbo interleaver for multiple third-generation wireless standards

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IEEE COMMUNICATIONS LETTERS 2003年第5期7卷 210-212页

作者： Shin, MC Park, IC Korea Adv Inst Sci & Technol Dept Elect Engn & Comp Sci Taejon 305701 South Korea

A software, turbo interleaver running. on,. a simd processor is presented for a turbo decoder supporting multiple 3G 3G wireless standards. To hide the timing overhead of interleaver changing, the interleaver generation is split into two parts, preprocessing and incremental on-the-fly generation. Applying the proposed approach, we implemented a W-CDMA and cdma2000 interleaver that generates one interleaved. address per cycle and occupies 10% area of the ROM implementation.

关键词： cdma2000 simd processor turbo interleaver W-CDMA

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Single chip programmable baseband ASSP for 5 GHz wireless LAN applications

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IEICE TRANSACTIONS ON ELECTRONICS 2002年第2期E85C卷 359-367页

作者： Kneip, J Weiss, M Drescher, W Aue, V Strobel, J Oberthür, T Bolle, M Fettweis, G Systemon AG D-01099 Dresden Germany

This paper presents the HiperSonic 1, a multi-standard, application-specific signal processor, designed to execute the baseband conversion algorithms in IEEE802.11a- and HIPERLAN/2-based 5 GHz wireless LAN applications. In contrast to widely existing, dedicated implementations. most of the computational effort here was mapped onto a configurable, data- and instruction-parallel DSP core. The core is supplemented by mixed signal A/D, D/A converters and hardware accelerators. Memory and register architecture, instruction set and peripheral interfaces of the chip were carefully optimized for the targeted applications, leading to a sound combination of flexibility, die area and power consumption. The 120 MHz, 7,6 million-transistor solution was implemented in 0.18 mum CMOS and performs IEEE802.11a or HiperLAN/2 compliant baseband processing at data rates up to 60 Mbit/s.

关键词： wireless LAN IEEE802.11 HiperLAN/2 programmable DSP simd processor WLAN ASSP

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Skeleton Particle-in-Cell Codes on Emerging Computer Architectures

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COMPUTING IN SCIENCE & ENGINEERING 2015年第2期17卷 47-52页

作者： Decyk, Viktor K. Univ Calif Los Angeles Los Angeles CA 90089 USA

If we define each supercomputer node as a parameterized abstract machine, then it's possible to design algorithms independently of hardware. Such an abstract machine could consist of a collection of vector processors, each with a small fast memory communicating via a larger global memory. Programming this type of machine will require ideas from the past as well as new concepts.

关键词： graphics processing units multiprocessing systems parallel architectures parallel machines program compilers simd processor computer architecture next generation processor parallel computer parameterized abstract machine skeleton particle-in-cell codes supercomputers Algorithm design and analysis Computer architecture High performance computing Parallel processing Program processors Scientific computing Supercomputers HPC concurrent programming distributed programming high-performance computing physics computer applications scientific computing

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An Embedded Vision Engine (EVE) for Automotive Vision Processing

An Embedded Vision Engine (EVE) for Automotive Vision Proces...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Mandal, Dipan Kumar Sankaran, Jagadeesh Gupta, Akshay Castille, Kyle Gondkar, Shraddha Kamath, Sanmati Sundar, Pooja Phipps, Alan Texas Instruments Inc Mohali India Texas Instruments Inc Dallas TX USA

ISBN: (纸本)9781479934324

This paper introduces Embedded Vision Engine (EVE) - a fully programmable, specialized vector processor architecture aimed at solving challenging Computer Vision applications encountered in Advanced Driver Assistance Systems (ADAS). The paper outlines the complexity of automotive vision applications, establishes why specialized architecture (like EVE) is needed and outlines the EVE architecture, its components and programming model. We present comparative benchmarks and provide an overview of many carefully crafted features of EVE for power management, inter processor communication, functional safety and software debug that helps in building a scalable, area-power efficient System-on-Chip (SoC) solutions for the cost, power and safety sensitive automotive vision space.

关键词： Vector processor simd processor processor Architecture Automotive Vision Computer Vision ADAS

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