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检索条件"主题词=SRAM array"
12 条 记 录,以下是1-10 订阅
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A leakage current suppression technique for cascade sram array in 55 nm CMOS technology
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Science China(Information Sciences) 2014年 第8期57卷 208-215页
作者: CHEN HongMing CHENG YuHua Shanghai Research Institute of Microelectronics (SHRIME) Peking University School of Information Science and Technology Peking University
Sub-threshold leakage is a major issue for low power circuits design,especially for sram design in ***-threshold leakage can be decreased by scaling down supply ***,this may dramatically increase the circuit *** this ... 详细信息
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Low Power and Noise Resistant 16X16 sram array Design using CMOS Logic and Differential Sense Amplifier
Low Power and Noise Resistant 16X16 SRAM Array Design using ...
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IEEE International Conference on Computing, Communication and Automation (ICCCA)
作者: Bisht, Rashmi Aggarwal, Priyanka Karki, Pooja Pande, Peyush Graph Era Univ Dept Elect & Commun Engn Dehra Dun Uttar Pradesh India
The main aim of this paper is to design a low power and noise resistant sram using Cadence (version 6.1.5) simulation tool. Standard gpdk180 library (i.e., 180nm technology node) is used for designing. A 16X16 sram ar... 详细信息
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Design of sram array using Reversible logic for an efficient SoC design
Design of SRAM array using Reversible logic for an efficient...
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International Conference on Inventive Computing and Informatics (ICICI)
作者: Sharma, Chinmay Chhabra, Varun Singh, Balwinder Pahuja, Hitesh Ctr Dev Adv Comp Acad Consultancy & Serv Div Mohali India
Recently, the power dissipation has become the prime concern with the system-on-chip (SOC) as technology scales. Further, the memory component of the design is as crucial, as it is energy consuming. The conventional a... 详细信息
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Design of a High Performance 1 Kb sram array Using Proposed Soft Error Hardened 12T sram Cell
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JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2022年 第14期31卷
作者: Kumar, R. Manoj Sridevi, P., V Andhra Univ Coll Engn A Dept ECE Visakhapatnam 530003 Andhra Pradesh India
The shrinking of technology node and supply voltage has a profound effect on various design metrics of the sram cell. Available sram designs in the literature suffer from half-select issue, increased write delay, leak... 详细信息
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Low Power and Noise Resistant 16X16 sram array Design using CMOS Logic and Differential Sense Amplifier
Low Power and Noise Resistant 16X16 SRAM Array Design using ...
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International Conference on Computing, Communication and Automation
作者: Rashmi Bisht Priyanka Aggarwal Pooja Karki Peyush Pande Dept. of Electronics & Communication Engineering Graphic Era University Dehradun India
The main aim of this paper is to design a low power and noise resistant sram using Cadence (version 6.1.5) simulation tool. Standard gpdkl80 library (i.e., 180nm technology node) is used for designing. A 16X16 sram ar... 详细信息
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sram arrays with Built-in Parity Computation for Real-Time Error Detection in Cache Tag arrays
SRAM Arrays with Built-in Parity Computation for Real-Time E...
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Design, Automation and Test in Europe Conference and Exhibition (DATE)
作者: Canal, Ramon Sazeides, Yiannakis Bramnik, Arkady Univ Politecn Cataluna Barcelona Spain Univ Cyprus Nicosia Cyprus Intel Corp Haifa Israel
This work proposes an sram array with built-in real-time error detection (RTD) capabilities. Each cell in the new RTD-sram array computes its part of the real-time parity of an sram array column on-the-fly. RTD based ... 详细信息
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Minimizing the Energy-Delay Product of sram arrays using a Device-Circuit-Architecture Co-Optimization Framework  16
Minimizing the Energy-Delay Product of SRAM Arrays using a D...
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53rd ACM/EDAC/IEEE Design Automation Conference (DAC)
作者: Shafaei, Alireza Afzali-Kusha, Hassan Pedram, Massoud Univ Southern Calif Dept Elect Engn Los Angeles CA 90089 USA
The objective of this paper is to minimize the energy-delay product of static random access memory (sram) arrays by using a device-circuit- architecture co-optimization framework. More specifically, at the device-leve... 详细信息
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Internal write-back and read-before-write schemes to eliminate the disturbance to the half-selected cells in srams
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IET CIRCUITS DEVICES & SYSTEMS 2018年 第4期12卷 460-466页
作者: Pasandi, Ghasem Pedram, Massoud Univ Southern Calif Dept Elect Engn Syst Los Angeles CA 90089 USA
In static random access memory (sram), some cells are not selected for writing, but due to the distribution of the word line signals in the sram array, their word line signal is activated. Therefore, they may be mista... 详细信息
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Low-power data encoding/decoding for energy-efficient static random access memory design
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IET CIRCUITS DEVICES & SYSTEMS 2019年 第8期13卷 1152-1159页
作者: Pasandi, Ghasem Mehrabi, Kolsoom Ebrahimi, Behzad Fakhraei, Sied Mehdi Afzali-Kusha, Ali Pedram, Massoud Univ Southern Calif Dept Elect & Comp Engn Los Angeles CA 90089 USA Univ Tehran Dept Elect & Comp Engn Tehran Iran Shiraz Univ Sch Elect & Comp Engn Shiraz Iran Islamic Azad Univ Sci & Res Branch Dept Elect & Comp Engn Tehran Iran
This study presents a new energy-efficient design for static random access memory (sram) using a low-power input data encoding and output data decoding stages. A data bit reordering algorithm is applied to the input d... 详细信息
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A continuation approach for computing parameter-dependent separatrices in sram cells
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APPLIED MATHEMATICAL MODELLING 2018年 64卷 106-120页
作者: Chavez, Joseph Paez Schreiter, Joerg Siegmund, Stefan Mayr, Christian Escuela Super Politecn Litoral Fac Nat Sci & Math Ctr Appl Dynam Syst & Computat Methods CADSCOM POB 09-01-5863 Guayaquil Ecuador Tech Univ Dresden Chair Highly Parallel VLSI Syst & Neuromorph Circ D-01062 Dresden Germany Tech Univ Dresden Dept Math Ctr Dynam D-01062 Dresden Germany
The continued scaling of CMOS semiconductor technology, together with the corresponding reduction of operating voltages, pose serious challenges for sram arrays regarding susceptibility to parameter variations, reduct... 详细信息
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