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A leakage current suppression technique for cascade sram array in 55 nm CMOS technology

Science China(Information Sciences) 2014年第8期57卷 208-215页

作者： CHEN HongMing CHENG YuHua Shanghai Research Institute of Microelectronics (SHRIME) Peking University School of Information Science and Technology Peking University

Sub-threshold leakage is a major issue for low power circuits design,especially for sram design in ***-threshold leakage can be decreased by scaling down supply ***,this may dramatically increase the circuit *** this paper,we propose a novel 6 T sram array structure with a switch module which operates in the near threshold region to reduce the leakage *** order to verify our proposed leakage reduction scheme,we designed and simulated an 8192 kB sram array based on a 16 KB single port sram cell memory model in 55 nm *** 6 T sram array instances are implemented in 55-nm 1P6M CMOS technology to measure the standby current of the proposed scheme as *** the proposed technique,we achieved 28.3%reduction for leakage current compared to traditional 6 T sram array,in standby mode where gate leakage is *** total penalty is 2%area increase and 1%speed reduction.

关键词： sram array standby leakage inactive mode low leakage SPICE

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Low Power and Noise Resistant 16X16 sram array Design using CMOS Logic and Differential Sense Amplifier

Low Power and Noise Resistant 16X16 SRAM Array Design using ...

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IEEE International Conference on Computing, Communication and Automation (ICCCA)

作者： Bisht, Rashmi Aggarwal, Priyanka Karki, Pooja Pande, Peyush Graph Era Univ Dept Elect & Commun Engn Dehra Dun Uttar Pradesh India

ISBN: (纸本)9781509016662

The main aim of this paper is to design a low power and noise resistant sram using Cadence (version 6.1.5) simulation tool. Standard gpdk180 library (i.e., 180nm technology node) is used for designing. A 16X16 sram array is designed having sram cells along with all peripheral components. Due to increased use of portable devices, power consumption has become an important parameter to be considered for efficient device design. Thus there is an urgent need of low power efficient memory design. This paper utilizes Full CMOS logic for sram cell design to effectively reduce static power dissipation as compared to resistive load inverter being used in previous designs. Peripheral components such as row decoder, precharge circuit, write driver circuit, sense amplifier and column decoder has been designed and assembled to form sram array. Differential type sense amplifier is used for noise reduction as it has the ability of common mode noise voltage rejection. Supply voltage of 1.8 V is considered. Transient responses for read and write operations for both logic-1 and logic-0 have been analyzed. Power consumption of 24.58 mW is measured for complete sram array.

关键词： CMOS sram array Cadence gpdk180 wordline write enable

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Design of sram array using Reversible logic for an efficient SoC design

Design of SRAM array using Reversible logic for an efficient...

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International Conference on Inventive Computing and Informatics (ICICI)

作者： Sharma, Chinmay Chhabra, Varun Singh, Balwinder Pahuja, Hitesh Ctr Dev Adv Comp Acad Consultancy & Serv Div Mohali India

ISBN: (纸本)9781538640319

Recently, the power dissipation has become the prime concern with the system-on-chip (SOC) as technology scales. Further, the memory component of the design is as crucial, as it is energy consuming. The conventional approach of circuit designing consumes a lot of power and occupies much area. Thus, the concept of reversible logic in circuit designing is garnering growing attention for low-power applications such as DNA computing, quantum computing and ultra-low power CMOS design. This paper proposes a reversible design of 4-bit 6-T sram array at 180nm-1.8V CMOS technology which achieves 8% reduction in energy consumption of the circuit. The designs are simulated on Cadence virtuoso 6.1.4 schematic editor. The present work also concludes with some insights on the operation of conventional sram 6-T cell and the feasibility of reversible logic.

关键词： System on Chip Reversible sram array CMOS power dissipation sram sram array

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Design of a High Performance 1 Kb sram array Using Proposed Soft Error Hardened 12T sram Cell

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JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2022年第14期31卷

作者： Kumar, R. Manoj Sridevi, P., V Andhra Univ Coll Engn A Dept ECE Visakhapatnam 530003 Andhra Pradesh India

The shrinking of technology node and supply voltage has a profound effect on various design metrics of the sram cell. Available sram designs in the literature suffer from half-select issue, increased write delay, leakage power, read power, and lower critical charge. Considering the above concerns, a new P12T sram cell was proposed incorporating the cross-point selection to remove half-select issue, adding the inverter between the storage nodes to enhance critical charge, High-Vth transistors in read path to reduce the read power and leakage power. The critical charge of P12T sram cell is 9.13% and 15.21% higher than the 8T and 10T sram cells, respectively, at 0.9V VDD. P12T sram cell has 41.61% and 21.4% decrease in read power than 8T and AS10T sram cells, respectively, at SS corner for 0.9V VDD. In P12T sram cell, write 1 PDP at worst case corner SS is 1.4x, 2.9x, 2.2x, 1.7x, and 3.3x lower than 8T, AS8T, AS10T, 10T, and 12T sram cells, respectively, at 0.9V VDD. Monte Carlo simulation has been done to study variability and half-select issue. 1Kb bit interleaving sram array is designed using P12T sram cell and 12T sram cell. 1Kb sram array using P12T sram cell has superior write PDP than 12T sram cell. Postlayout simulation has been carried out on all the sram cells to estimate different metrics in 45nm technology using the Cadence Virtuoso.

关键词： Critical charge write margin SNM power delay product leakage power sram array

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Low Power and Noise Resistant 16X16 sram array Design using CMOS Logic and Differential Sense Amplifier

Low Power and Noise Resistant 16X16 SRAM Array Design using ...

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International Conference on Computing, Communication and Automation

作者： Rashmi Bisht Priyanka Aggarwal Pooja Karki Peyush Pande Dept. of Electronics & Communication Engineering Graphic Era University Dehradun India

ISBN: (纸本)9781509016679

The main aim of this paper is to design a low power and noise resistant sram using Cadence (version 6.1.5) simulation tool. Standard gpdkl80 library (i.e., 180nm technology node) is used for designing. A 16X16 sram array is designed having sram cells along with all peripheral components. Due to increased use of portable devices, power consumption has become an important parameter to be considered for efficient device design. Thus there is an urgent need of low power efficient memory design. This paper utilizes Full CMOS logic for sram cell design to effectively reduce static power dissipation as compared to resistive load inverter being used in previous designs. Peripheral components such as row decoder, precharge circuit, write driver circuit, sense amplifier and column decoder has been designed and assembled to form sram array. Differential type sense amplifier is used for noise reduction as it has the ability of common mode noise voltage rejection. Supply voltage of 1.8 V is considered. Transient responses for read and write operations for both logic-1 and logic-0 have been analyzed. Power consumption of 24.58 mW is measured for complete sram array.

关键词： CMOS sram array Cadence gpdkl80 wordline write enable

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sram arrays with Built-in Parity Computation for Real-Time Error Detection in Cache Tag arrays

SRAM Arrays with Built-in Parity Computation for Real-Time E...

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Design, Automation and Test in Europe Conference and Exhibition (DATE)

作者： Canal, Ramon Sazeides, Yiannakis Bramnik, Arkady Univ Politecn Cataluna Barcelona Spain Univ Cyprus Nicosia Cyprus Intel Corp Haifa Israel

ISBN: (纸本)9783981926354

This work proposes an sram array with built-in real-time error detection (RTD) capabilities. Each cell in the new RTD-sram array computes its part of the real-time parity of an sram array column on-the-fly. RTD based arrays detect a fault right away after it occurs, rather than when it is read. RTD, therefore, breaks the serialization between data access and error detection and, thus, it can speed-up the access-time of arrays that use on-the-fly error detection and correction. The paper presents an analysis and optimization of an RTD-sram and its application to a tag array. Compared to a state-of-the-art tag array protection, the evaluated scheme has comparable error detection and correction strength and, depending on the array dimensions, the access time is reduced by 5% to 18%, energy by 20% to 40% and area up to 30%.

关键词： reliability sram array tag array error detection and correction real-time error detection (RTD)

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Minimizing the Energy-Delay Product of sram arrays using a Device-Circuit-Architecture Co-Optimization Framework 16

Minimizing the Energy-Delay Product of SRAM Arrays using a D...

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53rd ACM/EDAC/IEEE Design Automation Conference (DAC)

作者： Shafaei, Alireza Afzali-Kusha, Hassan Pedram, Massoud Univ Southern Calif Dept Elect Engn Los Angeles CA 90089 USA

ISBN: (纸本)9781450342360

The objective of this paper is to minimize the energy-delay product of static random access memory (sram) arrays by using a device-circuit- architecture co-optimization framework. More specifically, at the device-level, high-Vt FinFETs are adopted for the 6T sram cell, which significantly reduces the leakage power and improves static noise margins. However, due to the lower ON current, the bit-line delay of the read access is increased. Accordingly, at the circuit-level, the voltage level of assist circuits, and at the architecture-level (i.e., the array organization), key parameters of the sram array are jointly optimized to derive a design that results in the minimum energy-delay product point. By using the proposed optimization framework, for sram array capacities ranging from 1KB to 16KB, on average 59% lower energy-delay product with maximum 12% (and on average 9%) performance penalty is achieved.

关键词： sram array assist techniques energy-efficient memory design

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Internal write-back and read-before-write schemes to eliminate the disturbance to the half-selected cells in srams

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IET CIRCUITS DEVICES & SYSTEMS 2018年第4期12卷 460-466页

作者： Pasandi, Ghasem Pedram, Massoud Univ Southern Calif Dept Elect Engn Syst Los Angeles CA 90089 USA

In static random access memory (sram), some cells are not selected for writing, but due to the distribution of the word line signals in the sram array, their word line signal is activated. Therefore, they may be mistakenly written. Such cells are called half-selected cells. This study presents two schemes, one for single-ended and the other for differential sensing srams, to eliminate the half-selection disturbance. In the first proposed scheme, the content of the desired row of the sram array is read before the write operation and is written back on the corresponding write bitlines. This operation results in eliminating the possibility for noise to be written onto the half-selected cells. In the second scheme, a simple read operation is performed before the write operation. The authors applied their half-selection resilient schemes to 8 and 6T srams. Simulation results show that in the presence of radioactive particles, by applying their write-back scheme to 8T sram and their read-before-write scheme to the conventional 6T sram, the failure rate is reduced from an average of 56 and 20%, respectively, to 0. The proposed schemes do not degrade write-ability of the sram cells, and are bit-addressable. Moreover, their proposed schemes consume smaller amounts of power compared with their rivals.

关键词： sram chips sensor arrays internal write-back scheme read-before-write scheme half-selected cell static random access memory word line signal distribution sram array differential sensing half-selection disturbance elimination half-selection resilient scheme radioactive particle

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Low-power data encoding/decoding for energy-efficient static random access memory design

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IET CIRCUITS DEVICES & SYSTEMS 2019年第8期13卷 1152-1159页

作者： Pasandi, Ghasem Mehrabi, Kolsoom Ebrahimi, Behzad Fakhraei, Sied Mehdi Afzali-Kusha, Ali Pedram, Massoud Univ Southern Calif Dept Elect & Comp Engn Los Angeles CA 90089 USA Univ Tehran Dept Elect & Comp Engn Tehran Iran Shiraz Univ Sch Elect & Comp Engn Shiraz Iran Islamic Azad Univ Sci & Res Branch Dept Elect & Comp Engn Tehran Iran

This study presents a new energy-efficient design for static random access memory (sram) using a low-power input data encoding and output data decoding stages. A data bit reordering algorithm is applied to the input data to increase the number of 0s that are going to be written into the sram array. Using sram cells which are more energy-efficient in writing a '0' than a '1' benefits from this, resulting in a reduction in the total power and energy consumptions of the whole memory. The input data encoding is performed using a simple circuit, which is built of multiplexers and inverters. After the read operation, data will be returned back to its initial form using a low-power data decoding circuit. Simulation results in an industrial and a predictive CMOS technology show that the proposed design for sram reduces the energy consumption of read and write operations considerably for some standard test images as input data to the memory. For instance, in writing pixels of Lenna test image into this sram and reading them back, 15 and 20% savings are observed for the energy consumption of write and read operations, respectively, compared with the normal write and read operations in standard srams.

关键词： low-power electronics sram chips CMOS memory circuits encoding integrated circuit design energy-efficient design low-power input data encoding data bit reordering algorithm sram array sram cells energy consumption low-power data decoding circuit write read operations static random access memory design standard sram low-power data encoding-decoding power consumption multiplexers inverters complementary metal oxide semiconductor technology Lenna test image

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A continuation approach for computing parameter-dependent separatrices in sram cells

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APPLIED MATHEMATICAL MODELLING 2018年 64卷 106-120页

作者： Chavez, Joseph Paez Schreiter, Joerg Siegmund, Stefan Mayr, Christian Escuela Super Politecn Litoral Fac Nat Sci & Math Ctr Appl Dynam Syst & Computat Methods CADSCOM POB 09-01-5863 Guayaquil Ecuador Tech Univ Dresden Chair Highly Parallel VLSI Syst & Neuromorph Circ D-01062 Dresden Germany Tech Univ Dresden Dept Math Ctr Dynam D-01062 Dresden Germany

The continued scaling of CMOS semiconductor technology, together with the corresponding reduction of operating voltages, pose serious challenges for sram arrays regarding susceptibility to parameter variations, reduction of stability margins and reliability of read and write operations. One approach, alternative to various noise margin definitions, is to characterize the robustness of sram cells via the computation of stability boundaries, also referred to as separatrices. These curves define threshold voltages producing a flip in the logical state of an sram cell, which may lead to data loss due to disturbances, e.g. during read operations. The present work proposes a numerical approach to compute families of parameter-dependent separatrices based on path-following (continuation) methods, exploiting the geometric features of one-dimensional stable manifolds around saddle equilibria. The proposed approach is tested on an sram cell whose mathematical description is carried out in detail, based on the EKV (Enz, Krummenacher and Vittoz) equations for MOS transistors. In addition, the present work includes a comprehensive numerical study of the effect of parameter perturbations on separatrices, in a computationally efficient manner. (C) 2018 Elsevier Inc. All rights reserved.

关键词： sram array sram cell stability Stability boundary Numerical continuation Manifold approximation

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