Low-density parity-check (ldpc) codes are very efficient error control codes that are being considered for use in many next-generation communication systems. In this study low complexity soft-input, soft-output (SISO)...
详细信息
Low-density parity-check (ldpc) codes are very efficient error control codes that are being considered for use in many next-generation communication systems. In this study low complexity soft-input, soft-output (SISO) field programmable gate arrays (FPGA) implementations of a novel logarithmic sum-product (LogSP) iterativeldpcdecoder and a recently proposed simplified soft Euclidean distance (ssd) iterativeldpcdecoder are presented, and their complexities and performance are compared. These implementations operate over any choice of parity check matrix (including those randomly generated, structurally generated and either systematic or non-systematic) and can be parametrically adapted for any code rate. The proposed implementations are both of very low complexity, because they operate using only sums, subtractions, comparisons and look-up tables, which makes them particularly suitable for FPGA realisation. The ssddecoder has a lower implementation complexity than the LogSP ldpcdecoder and it also offers the advantage of not requiring knowledge of the channel signal-to-noise ratio, unlike most other ldpcdecoders.
暂无评论