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检索条件"主题词=Scheduling algorithm"

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Register File Energy Optimization for Snooping Based Clustered VLIW Architectures

引用

International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)

作者： Rahul Nagpal Y. N. Srikant Department of CSA Indian Institute of Science Bangalore India

Frequent accesses to the register file make it one of the major sources of energy consumption in ILP architectures. The large number of functional units connected to a large unified register file in VLIW architectures make power dissipation in the register file even worse because of the need for a large number of ports. High power dissipation in a relatively smaller area occupied by a register file leads to a high power density in the register file and makes it one of the prime hot-spots. This makes it highly susceptible to the possibility of a catastrophic heatstroke. This in turn impacts the performance and cost because of the need for periodic cool down and sophisticated packaging and cooling techniques respectively. Clustered VLIW architectures partition the register file among clusters of functional units and reduce the number of ports required thereby reducing the power dissipation. However, we observe that the aggregate accesses to register files in clustered VLIW architectures (and associated energy consumption) become very high compared to the centralized VLIW architectures and this can be attributed to a large number of explicit inter-cluster communications. Snooping based clustered VLIW architectures provide very limited but very fast way of inter-cluster communication by allowing some of the functional units to directly read some of the operands from the register file of some of the other clusters. In this paper, we propose instruction scheduling algorithms that exploit the limited snooping capability to reduce the register file energy consumption on an average by 12% and 18% and improve the overall performance by 5% and 11% for a 2-clustered and a 4-clustered machine respectively, over an earlier state-of-the-art clustered scheduling algorithm when evaluated in the context of snooping based clustered VLIW architectures.

关键词： VLIW Registers Power dissipation Energy consumption Computer architecture Packaging Cooling scheduling algorithm Delay High performance computing

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Resource Allocation for Downlink Multiuser Video Transmission Over Wireless Lossy Networks

Resource Allocation for Downlink Multiuser Video Transmissio...

引用

IEEE International Conference on Image Processing

作者： Ehsan Maani Peshala V. Pahalawatta Randall Berry Thrasyvoulos N. Pappas Aggelos K. Katsaggelos Electrical Engineering and Computer Science Department Northwestern University Evanston IL USA

The emergence of 3G and 4G wireless networks brings with it the possibility of streaming high quality video content on-demand to mobile users. Wireless video applications require appropriate scheduling techniques that make use of the specific characteristics of video content, as well as the well known gains from multiuser diversity. While fast and frequent channel feedback is available in the new generation of wireless networks, the channel estimates cannot be perfect, and channel losses should be taken into account in the packet scheduling and resource allocation. The proposed scheme is formulated as a joint optimization over the resource allocation and channel loss protection, in order to minimize the distortion of the received video sequences. The distortion is a function of the packets deliberately dropped at the transmission queue due to congestion, as well as of random channel losses. The scheme makes use of a packet prioritization strategy that orders video packets based on their contribution to reducing the expected distortion of the received video sequence. Simulation results show that the proposed technique significantly outperforms content-independent packet scheduling schemes.

关键词： Resource management Downlink Propagation losses Video on demand Wireless networks scheduling algorithm Video sequences Streaming media Feedback Protection

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Design and Performance of FDL Buffers in Optical Switches

Design and Performance of FDL Buffers in Optical Switches

引用

International Conference on Transparent Optical Networks

作者： Zvi Rosberg Hai Le Vu CSIRO ICT Centre Sydney NSW Australia Swinburne University VIC Australia

ISBN: (纸本)142441248X

A key technique for reducing packet blocking in optical switches is by temporarily buffering packets in fiber delay lines (FDLs). The packet blocking probability depend on the FDLs design as well as on how packets are scheduled to the FDL buffers. This study compares between the blocking probabilities of the following design and buffer scheduler options: (i) input vs output port FDLs; (ii) shared vs port-dependent FDLs; (iii) forward vs feedback FDLs; (iv) variable vs fixed size FDLs; and (v) FIFO vs non-overlapping buffer schedulers. The comparison results reveals several interesting facts. The first one is that feedback FDL design can reduce the number of required buffers by 75% compared with a forward FDL design. Another observed fact is that fixed-size FDLs is very wasteful, specifically, the length of a fixed size FDL has no affect on the blocking probability. The third observation is that a non-overlapping buffer scheduler can reduce the number of required FDLs by 30% compared with a FIFO scheduler.

关键词： Optical design Optical buffering Optical switches Optical feedback Delay lines scheduling algorithm Australia Output feedback All-optical networks Optical fiber communication

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The Integration of Multimedia Process Unit into an Embedded Processor

The Integration of Multimedia Process Unit into an Embedded ...

引用

IEEE International Conference on Integration Technology (ICIT)

作者： Xiaoping Huang Xiaoya Fan Shengbing Zhang Aviation Microelectronic Center 769# Northwestern Polytechnical University Xi'an China

To speed up the processing of the multimedia data, an independent multimedia process unit can be integrated into the embedded processor by SOC technology. Based on one existing embedded processor, the authors design the IP core of the multimedia process unit of the processor. The IP can process two multimedia instructions per cycle. It has six pipeline stages. The complex logic of the dynamic scheduling algorithm is allocated into different stage to alleviate the timing pressure. According to the multimedia benchmarks, the IP core can achieve higher performance with optimal timing and area, so it can improve the whole performance of the embedded processor.

关键词： Timing Streaming media Registers Microelectronics Pipelines Process design Logic Dynamic scheduling Heuristic algorithms scheduling algorithm

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Flow Balancing Hardware for Parallel TCP Streams on Long Fat Pipe Network

Flow Balancing Hardware for Parallel TCP Streams on Long Fat...

引用

International Conference on Future Generation Communication and Networking (FGCN)

作者： Yutaka Sugawara Mary Inaba Kei Hiraki Graduate School of Information Science and Technology University of Tokyo Tokyo Japan

ISBN: (纸本)9780769530482;0769530486

Parallel TCP streams are used for data transfer between clusters in today's high performance applications. When parallel TCP streams are used on LFN, part of streams fail to get enough bandwidth because of congestion generated by the parallel TCP streams themselves [5]. As a result, data transfer throughput is bottlenecked by the slow streams. In this paper, we propose the Stream Harmonizer that schedules packet transmission of parallel TCP streams to balance the bandwidth. The purpose of the Stream Harmonizer is to reduce the congestion that is generated by the parallel TCP streams themselves to improve the performance of the slow streams. The Stream Harmonizer reduces congestion by reducing the bandwidth of fast streams by in creasing the round trip time (RTT) of them. A hardware based lightweight scheduling algorithm is used to realize wire-rate intensive scheduling at high-speed backbone network. The Stream Harmonizer is able to schedule packets without exchanging additional information with end hosts. In this paper, we implement the Stream Harmonizer using TGNLE-1, an FPGA (Field Programmable Gate Array) based 10Gbit Ethernet experimental testbed. In addition, we evaluate the Stream Harmonizer using an FPGA based network emulator.

关键词： Hardware Bandwidth Throughput Field programmable gate arrays Ethernet networks TCPIP Testing Reservoirs Information science scheduling algorithm

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Dynamic Power Management with Hybrid Power Sources 07

Dynamic Power Management with Hybrid Power Sources

引用

Design Automation Conference

作者： Jianli Zhuo Chaitali Chakrabarti Kyungsoo Lee Naehyuck Chang Department of Electrical Engineering Arizona State University Tempe AZ USA School of Computer Science and Engineering Seoul National University Seoul South Korea

ISBN: (纸本)9781595936271

DPM (Dynamic Power Management) is an effective technique for reducing the energy consumption of embedded systems that is based on migrating to a low power state when possible. While conventional DPM minimizes the energy consumption of the embedded system, it does not utilize the properties of the power source. Alternative power sources such as fuel cells (FCs) have substantially different power and efficiency characteristics that have to be taken into account while developing policies that maximize their operational lifetime. In this paper, we present a new DPM policy for embedded systems powered by FC based hybrid source. We develop an optimization framework that explicitly considers the FC system efficiency and is aimed at minimizing the fuel consumption. Next we apply this optimization framework on top of a prediction based DPM policy to develop a new fuel-efficient DPM scheme. The proposed algorithm was applied to a real trace based MPEG encoding example and demonstrated up to 32% more system lifetime extension compared to a competing scheme.

关键词： Energy management Embedded system Batteries Power system management Energy consumption Engineering management Fuel cells scheduling algorithm Packaging Computer science

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Resource Allocation for a Life Science Automation Line: a Petri nets Approach

Resource Allocation for a Life Science Automation Line: a Pe...

引用

IEEE International Conference on Automation Science and Engineering (CASE)

作者： Tao Hong Mo-Yuen Chow Advanced Diagnosis Automation and Control (ADAC) Laboratory Electrical & Computer Engineering Department North Carolina State University NC USA

High-throughput screening (HTS) processes have been increasingly used in the life sciences area for diverse bio-chemical experiments. This paper investigates the resource allocation issue of scheduling HTS processes under multiple constraints including operation constraints, resource constraints, starvation constraints and multi-experiment constraints. We first use timed transition Petri nets (PN) to model the HTS processes. We then illustrate the transition variant property of the PN model, and propose an efficient best-first (E-BF) algorithm combined with PN execution to find the schedule. Finally we apply the E-BF algorithm to three typical HTS experimental processes under different resource constraints and compare the E-BF algorithm with a traditional best-first (BF) algorithm as case studies. The results show that the E-BF algorithm can be used to allocate resources for HTS processes properly and can easily be more efficient than the BF algorithm when applied to transition variant PN.

关键词： Resource management Petri nets High temperature superconductors scheduling algorithm Job shop scheduling Mathematical model Humans Robotics and automation Automatic control USA Councils

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Low-Capture-Power Test Generation by Specifying A Minimum Set of Controlling Inputs

Low-Capture-Power Test Generation by Specifying A Minimum Se...

引用

The 16th Asian Test Symposium(第十六届亚洲测试学术会议)

作者： Nan-Cheng Lai Sying-Jyan Wang Department of Computer Science National Chung-Hsing University Taichung 402 Taiwan ROC

We propose a low capture power test generation method to address the capture power issue in scan-based designs. The proposed approach tries to find a minimum set of input values to determine the output values and thus leave as many X-bits in the input side as possible. These X-bits can be assigned to values that minimize capture power In the proposed method, the global information of circuit structure is considered to reduce the appearance of unnecessary inconsistent assignments in X-filling procedure. As a result, the algorithm runs similar to previous methods in worst case. Experimental results show that the proposed method provides a better result than previous method and the approach can be adopted with any other advanced test pattern generator.

关键词： Circuit testing Energy consumption Power generation Test pattern generators Design for testability Flip-flops Nondestructive testing Computer science scheduling algorithm Built-in self-test

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Multi-Speed DVS algorithms for Periodic Tasks with Non-Preemptible Sections

Multi-Speed DVS Algorithms for Periodic Tasks with Non-Preem...

引用

IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)

作者： Jaewoo Lee Kern Koh Chang-Gun Lee School of Computer Science and Engineering Seoul National University Seoul South Korea

Reducing energy consumption is important for mobile embedded systems and one of its solutions is dynamic voltage scaling (DVS). In this paper, we examine how to achieve further energy saving for periodic real-time tasks with non-preemptible sections on EDF algorithm by using DVS. Previous algorithms use two speed levels to deal with run-time blocking situation. However, this paper proposes a multi-speed algorithm that exploits various speed levels depending on specific blocking situation to minimize energy consumption. Moreover, it also presents an enhanced multi-speed algorithm that further reduces the energy dissipation by dropping the speed level early and considering only remaining blocking time to compute a lower speed. We induced feasibility conditions for our algorithms and proved them. The experiments show that proposed algorithms achieve up to 70.8% energy saving compared to previous algorithms.

关键词： Voltage control Energy consumption Dynamic voltage scaling scheduling algorithm Resource management Medical services Embedded system Runtime Energy efficiency Clocks

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Utilization-Bound Based Schedulability Analysis of Weighted Round Robin Schedulers

Utilization-Bound Based Schedulability Analysis of Weighted ...

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Real-Time Systems Symposium (RTSS)

作者： Jianjia Wu Jyh-Charn Liu Wei Zhao Department of Computer Science Texas A and M University USA

Schedulability analysis is a cornerstone of modern real-time scheduling theory development. Utilization- bound based schedulability test is considered one of most efficient and effective schedulability tests, because of its extremely low runtime overhead. Deriving the utilization bound for a given real-time system has, nevertheless, been a challenging task as it usually requires comprehensive modeling and understanding of the system and payload tasks. This paper is focused on deriving utilization bounds for weighted round robin schedulers. We demonstrate how to establish a unified modeling framework and then use it to derive utilization bounds. We obtain the optimal parameter selection that maximizes the utilization bound, then compare the new bound with those of fixed priority schedulers, and timed token ring schedulers. The new bound is further extended to systems with sporadic job requests. We argue that our modeling framework is highly versatile, and hence, can be easily tailored for analysis of other types of real-time systems.

关键词： Round robin Real time systems Processor scheduling scheduling algorithm Payloads System testing Runtime Token networks Load management Computer science

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