Sphere Decoding (SD) algorithm has emerged as a highly effective detection scheme for Multiple-Input Multiple-output (MIMO) systems. It offers a near maximum likelihood accuracy with reduced complexity. Despite this, ...
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ISBN:
(纸本)9781479916054
Sphere Decoding (SD) algorithm has emerged as a highly effective detection scheme for Multiple-Input Multiple-output (MIMO) systems. It offers a near maximum likelihood accuracy with reduced complexity. Despite this, there is a constant demand of even low complexity SD algorithms. This paper presents the FPGA implementation of schnorr-euchner SD algorithm with Early Termination (ET) scheme for uncoded multiple-input multiple output system. The ET scheme reduces the complexity of the decoder. The proposed decoder is designed for 4x4 Binary Phase Shift Keying (BPSK) MIMO system. The trade-off between the Bit Error Rate (BER) performance and the computational complexity is discussed. To compute the computational complexity synthesis of the proposed design is done on Xilinx Virtex 5 XC5VLX30T and Spartan 6 XC6SLX25T. An exhaustive comparison on the basis of resources utilized and frequency (MHz) at which the design can run is done on both the FPGAs.
K-best schnorr-euchner (KSE) decoding algorithm is proposed in this paper to approach near-maximum-likelihood (ML) performance for multiple-input-multiple-output (MIMO) detection. As a low complexity MIMO decoding alg...
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K-best schnorr-euchner (KSE) decoding algorithm is proposed in this paper to approach near-maximum-likelihood (ML) performance for multiple-input-multiple-output (MIMO) detection. As a low complexity MIMO decoding algorithm, the KSE is shown to be suitable for very large scale integration (VLSI) implementations and be capable or supporting soft outputs. Modified KSE (MKSE) decoding algorithm is further proposed to improve the performance of the soft-output KSE with minor modifications. Moreover, a VLSI architecture is proposed for both algorithms. There are several low complexity and low-power features incorporated in the proposed algorithms and the VLSI architecture. The proposed hard-output KSE decoder and the soft-output MKSE decoder is implemented for 4 x 4 16-quadrature amplitude modulation (QAM) MIMO detection in a 0.35-mu m and a 0.13-mu m CMOS technology, respectively. The implemented hard-output KSE chip core is 5.76 mm(2) with 91 K gates. The KSE decoding throughput is up to 53.3 Mb/s with a core power consumption of 626 mW at 100 MHz clock frequency and 2.8 V supply. The implemented soft-output MKSE chip can achieve a decoding throughput of more than 100 Mb/s with a 0.56 mm(2) core area and 97 K gates. The implementation results show that it is feasible to achieve near-ML performance and high detection throughput for a 4 x 4 16-QAM MIMO system using the proposed algorithms and the VLSI architecture with reasonable complexity.
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