In order to give full play to the advantages of software defined chip hardware architecture, this paper designs a configuration mechanism of software defined chip applied in the field of signalprocessing. Firstly, th...
详细信息
ISBN:
(纸本)9781665487900
In order to give full play to the advantages of software defined chip hardware architecture, this paper designs a configuration mechanism of software defined chip applied in the field of signalprocessing. Firstly, this paper designs the configuration line execution iteration of PE (processing Element); Secondly, the iteration times of PE top layer are designed; Thirdly design the number of PEA (processing element array) top-level iterations; Finally, the implementation of matrix multiplication algorithm is used to analyze the hardware design results. Through simulation, the results show that, compared with TI c66x DSP, the clock cycle required to execute the same algorithm is reduced from 15325 to 200; The power consumption is reduced from 1092 mW to 420 mW, and the processing speed and power consumption are better than those of TI c66x DSP.
Several types of heart malfunctions are usually caused by heart attack, rhythm disturbances and pathological degenerations. Unfortunately large groups of people are affected by this problem. The main goal of this pape...
详细信息
Several types of heart malfunctions are usually caused by heart attack, rhythm disturbances and pathological degenerations. Unfortunately large groups of people are affected by this problem. The main goal of this paper is to compare the direct and inverse ECG signalprocessing methods, and to define an optimal solution in different circumstances. Due to the high number of unknown parameters, both algorithms apply stochastic processing methods. None of the processing ways can give us "best" results. The performance is determined by the known and unknown parameters. In most cases both methods can contribute to the optimal solution.
This paper quantifies the performance difference between custom and generic hardware algorithm implementations, illustrating the challenges that are involved in Body Area Network signalprocessing implementations. The...
详细信息
This paper quantifies the performance difference between custom and generic hardware algorithm implementations, illustrating the challenges that are involved in Body Area Network signalprocessing implementations. The potential use of analogue signalprocessing to improve the power performance is also demonstrated.
Covariance shaping least squares estimator is a new kind of linear estimator based on covariance shaping in quantum signalprocessing (QSP) *** this paper,we apply the covariance shaping least squares (CSLS) estimator...
详细信息
Covariance shaping least squares estimator is a new kind of linear estimator based on covariance shaping in quantum signalprocessing (QSP) *** this paper,we apply the covariance shaping least squares (CSLS) estimator to the detection of MIMO systems that leads to a new detection algorithm,covariance shaping MIMO detection *** derive the formalism of covariance shaping MIMO detection algorithm,and analyze its performance by numerical *** results show that the performance of system is better than that of detection algorithm with Zero-forcing and MMSE solutions,and the objective covariance matrix plays an important role in the proposed scheme
In an effort to produce more efficient means of transforming new algorithm concepts into working models, this paper describes the development of a digital signalprocessing workstation accepting input entirely in grap...
详细信息
In an effort to produce more efficient means of transforming new algorithm concepts into working models, this paper describes the development of a digital signalprocessing workstation accepting input entirely in graphic form. This Graphic Oriented signalprocessing Language (GOSPL) accepts flow graph information in block diagram form using a mouse input device. The researcher uses the mouse to describe graph connections and create function blocks in the flow graph by selecting them from a menu. The system executes a broad class of flow graphs and provides virtual instruments to monitor signals throughout the graph during real-time execution.
The paper presents a high speed and a high resolution pipelined A/D converter relying on a current mode technique. The A/D converter structure is composed of current mode building blocks. All building blocks have been...
详细信息
The paper presents a high speed and a high resolution pipelined A/D converter relying on a current mode technique. The A/D converter structure is composed of current mode building blocks. All building blocks have been designed, then manufactured, in CMOS AMS 0.8 /spl mu/m technology and measured to verify the proposed concept.
A theoretical and algorithmic framework is proposed for optimal identification of rational transfer function parameters of discrete-time linear systems from input-output (IO) data. The nonlinear criterion is theoretic...
详细信息
A theoretical and algorithmic framework is proposed for optimal identification of rational transfer function parameters of discrete-time linear systems from input-output (IO) data. The nonlinear criterion is theoretically decoupled into a purely linear problem for estimating the optimal numerator and a nonlinear problem for the optimal denominator. The proposed decoupled approach has reduced computational requirements when compared with existing algorithms that estimate the parameters simultaneously.
It is noted that signalprocessing designs for real-time large-scale systems are increasingly confronted with two conflicting objectives. The traditional objective of optimal design in low signal-to-noise ratio enviro...
详细信息
It is noted that signalprocessing designs for real-time large-scale systems are increasingly confronted with two conflicting objectives. The traditional objective of optimal design in low signal-to-noise ratio environments is confronted with the need for simplicity in implementation and speed of computation. The inclusion of high throughput and efficient hardware utilization as constraints on digital filter designs is considered. In particular, implementation of the design via an array processor is introduced. The concept of fast processing becomes synonymous with high throughout and efficient implementation on such a device. Using an array interpretation of the FFT structure, the retention of this highly efficient structure in a general design setting is demonstrated. For a typical signal extraction design, a constrained least-squares minimization is introduced to determine optimal enhancing filters with highly efficient array implementation.< >
In this paper, we consider a class of N-th order lattice filter with gains as an extension to the traditional lattice filter structures and develop analysis and synthesis of such filters. In the analysis-synthesis par...
详细信息
In this paper, we consider a class of N-th order lattice filter with gains as an extension to the traditional lattice filter structures and develop analysis and synthesis of such filters. In the analysis-synthesis parts, we present recursive methods to derive the input-output transfer function of the filter in terms of parameters of the lattice structure such as the time delay, gains, transmission and reflection coefficients and vice versa. Stability of the filter is analyzed and an algorithm to test the stability is proposed. This class of MIMO lattice filters with adjustable gains models integrated photonic devices under development in our labs for optical communication and high speed signalprocessing applications. Our signalprocessing approach to characterizing this type of lattice structures can also be used in filter realization by VLSI, FPGA, or programmable processors for acoustic or speech applications
暂无评论