Parallel matrix multiplication algorithms (based on the common data distribution formats) used in pattern recognition, image processing, and signalprocessing applications are discussed. A novel algorithm is introduce...
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Parallel matrix multiplication algorithms (based on the common data distribution formats) used in pattern recognition, image processing, and signalprocessing applications are discussed. A novel algorithm is introduced and is shown to be the fastest one for a determined class of applications. The algorithms are analyzed for performance as a function of array dimension, data distribution formats, and the architecture of the computer upon which the algorithms are executed. Performance bounds and speedups (linear in the number of processors) are established. The results of the analysis are given both as characterizations of executions on selected classes of architectures and also in the form of theorems which establish the relative performance of the algorithms across classes of data distributions and architectures.< >
In this paper we discuss two kinds of ill-posed problems in signalprocessing, that is, in detail, reconstructing compactly supported signals in the Fourier transform and solving the convolution equation with analytic...
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In this paper we discuss two kinds of ill-posed problems in signalprocessing, that is, in detail, reconstructing compactly supported signals in the Fourier transform and solving the convolution equation with analytic kernel. Having analyzed the essential reason of ill-posedness for these problems, we present some stabilized algorithms, which cure the ill-posedness, to recover the approximate solution. Finally numerical experiments show the efficiency and fast convergence of these algorithms.
Traditional digital signalprocessing technology based on DSP and FPGA is more suitable for real-time signalprocessing, and is limited by data scale and frequency resolution, making it unsuitable for offline data pro...
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ISBN:
(纸本)9781728190198
Traditional digital signalprocessing technology based on DSP and FPGA is more suitable for real-time signalprocessing, and is limited by data scale and frequency resolution, making it unsuitable for offline data processing, analysis and mining under large-scale data Application. At present, the industrial big data analysis platform can use Spark as a calculation engine for real-time signalprocessing and offline signalprocessing acceleration, but the analysis platform lacks mathematical calculation solutions such as digital signalprocessing suitable for distributed parallel calculation engines. This article is based on time the parity decomposition is selected, and the fast Fourier transform is realized by MATLAB software. Based on an example of the application of the compiled FFT source program, this article analyses the frequency spectrum of discrete-time and continuous-time signals of limited length.
Square-root algorithms have use in certain areas of digital signalprocessing. However, they are characterized as being non-linear in nature and hence their analysis is not straight-forward. This paper examines two su...
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ISBN:
(纸本)9781509067497
Square-root algorithms have use in certain areas of digital signalprocessing. However, they are characterized as being non-linear in nature and hence their analysis is not straight-forward. This paper examines two such algorithms and shows that the convergence is guaranteed provided the closed-loop discrete-time system is stable, but that the upper limit on stability is determined by the values of the square-root coefficients themselves. The analysis is quite classical but also requires a link between Toeplitz matrices and polynomials to progress further.
New types of discrete-time automatic gain control (AGC) circuits are proposed. The AGCs are based on iterative processes, and both feedforward and feedback structures are considered for two different signal energy det...
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New types of discrete-time automatic gain control (AGC) circuits are proposed. The AGCs are based on iterative processes, and both feedforward and feedback structures are considered for two different signal energy detectors: mean absolute deviation (MAD) and root mean square (RMS). The different algorithms were implemented on a digital signal processor, and experimental results are presented.< >
Linearly constrained LMS adaptive filter algorithms are considered for digital processing of 50/60 Hz line-frequency signals. The constraints are set such that the primary sinusoidal waveform is guaranteed to pass the...
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Linearly constrained LMS adaptive filter algorithms are considered for digital processing of 50/60 Hz line-frequency signals. The constraints are set such that the primary sinusoidal waveform is guaranteed to pass the filter unaltered, and the adaptation is used to dynamically optimize the noise attenuation properties. In order to reduce the computational complexity of the constrained algorithm, selective coefficient updating is used, and the update formulas are derived accordingly. The approach is efficient in suppressing noise and harmonics in applications such as reactive power estimation and zero-crossing detection.
Several modified Least Mean Square (LMS) algorithms are studied in order to improve the rate of convergence of the regular LMS algorithm. The performance of these modified LMS algorithms is evaluated by simulations. I...
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ISBN:
(纸本)0780313852
Several modified Least Mean Square (LMS) algorithms are studied in order to improve the rate of convergence of the regular LMS algorithm. The performance of these modified LMS algorithms is evaluated by simulations. It shows that the error feedback LMS algorithm converges much faster then all other modified LMS algorithms including regular LMS algorithm.< >
Adaptive beamforming (ABF) methods typically yield beam patterns that contain regions of high sidelobe gain. This can become a major problem when the platform is mobile with respect to noise sources. Real world ABF sy...
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Adaptive beamforming (ABF) methods typically yield beam patterns that contain regions of high sidelobe gain. This can become a major problem when the platform is mobile with respect to noise sources. Real world ABF systems demand some sort of sidelobe control or stabilisation - one such approach is via penalty function methods. Computational speed is an important issue and their exists a requirement for computationally efficient methods of calculating penalty functions. One such method is described in this paper.
To reduce computation time in a multiprocessor environment the efficient configuration and utilization of hardware components is necessary. It requires both a restructuring of the considered algorithms and a reconfigu...
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To reduce computation time in a multiprocessor environment the efficient configuration and utilization of hardware components is necessary. It requires both a restructuring of the considered algorithms and a reconfiguration of the corresponding machine architectures. A transformation system is presented, which uses computation graphs as a representation of both the algorithmic structure and the processor configuration. The system is able to rewrite the computation graph automatically, dependent on the available hardware resources. In this paper the design strategy for algorithms and machine models is illustrated by the DFT. Several models for the algorithm are discussed. Finally the results of time and hardware complexity with regard to the different graph structures and machine architectures are presented.
The authors present the implementation of a generic dynamic programming algorithm on array processors. A dynamic programming (DP) chip is proposed to speed up the processing of the dynamic programming tasks in many ap...
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The authors present the implementation of a generic dynamic programming algorithm on array processors. A dynamic programming (DP) chip is proposed to speed up the processing of the dynamic programming tasks in many applications, including the Viterbi algorithm, the boundary following algorithm, the dynamic time warping algorithm, etc. By adopting a torus interconnection network, an internal/external dual buffer structure, and a multilevel pipelining design, a performance of several GOPS per DP chip is expected. Both the dedicated hardware design and the data low control of the DP chip are discussed.< >
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