This paper describes the implementation of a custom DSP system to accelerate image processingalgorithms used in the field of digital holography. The system, implemented on an FPGA platform, is intended for real-time ...
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This paper describes the implementation of a custom DSP system to accelerate image processingalgorithms used in the field of digital holography. The system, implemented on an FPGA platform, is intended for real-time reconstruction of images captured on a large image sensor. Due to the large amount of processing information, it is not possible to perform a HDL simulation of a complete image reconstruction in reasonable time. Instead, a reconfigurable solution is being used for full scale image reconstruction, exhaustive testing of the functionality and for connecting the accelerator to external components, i.e. the image sensor, monitor output device and high-speed memory banks.
Two digital signal processing algorithms for frequency deviation measurement are introduced. The algorithms are derived using a new signalprocessing scheme based on quadratic forms of signal samples. These algorithms...
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Two digital signal processing algorithms for frequency deviation measurement are introduced. The algorithms are derived using a new signalprocessing scheme based on quadratic forms of signal samples. These algorithms provide high measurement accuracy over a wide range of frequency changes. One is designed for measurements of small deviations of the nominal frequency, whereas the other one measures off-nominal frequency deviations. The performance of the algorithms is evaluated using computer simulation tests.< >
Design teams are increasingly looking for design flows that can rapidly lead to high performance and low power implementation of DSP algorithms. Model-based design can satisfy this requirement, but it must be (1) coup...
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Design teams are increasingly looking for design flows that can rapidly lead to high performance and low power implementation of DSP algorithms. Model-based design can satisfy this requirement, but it must be (1) coupled with efficient high-level synthesis support in order to provide good Quality of Results, and (2) controlled to derive the desired area/performance/throughput trade-off. We present a semi-automatic design flow for rapid high level synthesis-based hardware design space exploration starting from Simulink digital signalprocessing models. We illustrate our flow with a realistically complex signalprocessing algorithm for estimating the direction of arrival of a sound source. We show how one can start from a functionally validated fixed point model in Simulink and then go through a relatively simple design flow for hardware synthesis and automatic design space exploration, obtaining a very efficient hardware implementation that is competitive with the RTL implementation generated by another commercial model-based design tool.
In this paper, we explore the use of multi-stage adaptation algorithms for a variety of adaptive filtering applications where the structure of the underlying process to be estimated is unknown. These algorithms are &q...
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In this paper, we explore the use of multi-stage adaptation algorithms for a variety of adaptive filtering applications where the structure of the underlying process to be estimated is unknown. These algorithms are "multi-stage" in that they comprise multiple adaptive filtering algorithms that operate in parallel on the observation sequence, and adaptively combine the outputs of this first stage to form an overall signal estimate. Several examples of this class of algorithms are demonstrated and analyzed in both a deterministic and stochastic context with respect to their convergence and mean squared error. The first example of this class, a "universal" linear predictor, was recently introduced and shown to asymptotically achieve the performance of the best linear predictor for each sequence, (up to some maximal order). Two new algorithms have been developed that generalize this universal linear predictor, and explore the use of the LMS algorithm in each stage of adaptation. Each of these algorithms are compared through theoretical analysis of their behavior.
This paper reviews established and emerging parallel technologies, which are employed to enhance the performance of digital signal processing algorithms. Special attention is paid to algorithms with applications in me...
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ISBN:
(数字)9781728121949
ISBN:
(纸本)9781728121956
This paper reviews established and emerging parallel technologies, which are employed to enhance the performance of digital signal processing algorithms. Special attention is paid to algorithms with applications in medical imaging. Parallel implementations of some of the most commonly used algorithms, such as Fourier transforms, convolution and cross-correlation are discussed. Parallel optimization of a newly introduced method in optical coherence tomography is presented. Its performance, in terms of latency, is presented and discussed.
The authors describe a novel digital filtering algorithms for the processing and representation of signals using polynomial splines. The classical polynomial spline interpolation problem is considered. It is found tha...
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The authors describe a novel digital filtering algorithms for the processing and representation of signals using polynomial splines. The classical polynomial spline interpolation problem is considered. It is found that it can be solved efficiently by recursive digital filtering. This result also yields a simple procedure for signal differentiation. Filters that efficiently solve the problem of smoothing spline approximations are derived. This technique is a regularized version of spline interpolation and is therefore less sensitive to noise. It is applied to the design of a robust edge detection algorithm with an adjustable scale parameter. A filtering/sampling algorithm for least squares spline approximation is described. This data reduction technique is applied to the generation of a cubic spline image pyramid that is found to compare favorably with the Gauss/Laplace pyramid.< >
This paper presents a complete methodology for the automatic synthesis of VLSI architectures used in digital signalprocessing. Most signal processing algorithms have the form of an n-dimensional nested loop with unit...
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This paper presents a complete methodology for the automatic synthesis of VLSI architectures used in digital signalprocessing. Most signal processing algorithms have the form of an n-dimensional nested loop with unit uniform loop carried dependencies. We model such algorithms with generalized UET grids. We calculate the optimal makespan for the generalized UET grids and then we establish the minimum number of systolic cells required for achieving the optimal makespan. We present a complete methodology for the hardware synthesis of the resulting architecture, based on VHDL. This methodology automatically detects all necessary computation and communication elements and produces optimal layouts. The complexity of our proposed scheduling policy is completely independent of the size of the nested loop and depends only on its dimension, thus being the most efficient (in terms of complexity) known to us. All these methods were implemented and incorporated in an integrated software package which provides the designer with a powerful parallel design environment, from high level signalprocessing algorithmic specifications to low-level (i.e., actual layouts) optimal implementation. The evaluation was performed using well-known algorithms from signalprocessing.
Field Programmable Gate Array (FPGA) architectures have emerged as an alternative means of implementing complex logic circuits providing rapid manufacturing turnaround time and low prototyping costs. This paper presen...
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Field Programmable Gate Array (FPGA) architectures have emerged as an alternative means of implementing complex logic circuits providing rapid manufacturing turnaround time and low prototyping costs. This paper presents a new FPGA architecture suitable for the application specific signal processing algorithms and Wafer-Scale integration (WSI) Technology. The architecture must be designed for versatility, flexibility, high speed, improved logic density, and defect tolerance. The proposed FPGA architecture consists of 2 dimensional array of programmable logic elements based on look-up table, interconnection resources, and input/output (I/O) blocks. The architectural style is similar to the one used in XILINX FPGA architecture. A key variation from the commonly used FPGA is the dual switching scheme employed in the proposed architecture. The design methodology, the design tools, and results obtained by using a Segmented Channel Routing algorithm to map on it a 16 bit parallel multiplier, are presented.
Motivated by recent advances made in VLSI and VLSI-based systems, we describe the functional programming(FP) style as proposed by Backus [1]. Comparative studies are made by coding simple algorithms in a conventional ...
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Motivated by recent advances made in VLSI and VLSI-based systems, we describe the functional programming(FP) style as proposed by Backus [1]. Comparative studies are made by coding simple algorithms in a conventional language and in FP. We find that the methodologies involved in the two approaches are different; conventional languages require thinking at an object level while FP styles favour a more hierarchical formalization. The paper also discusses some limitations of FP styles that will have to be remedied.
Difficulties concerning the detection of TBMs result from their radial speed, which is higher than a fighter's, and radar cross section (RCS) value, which is lower than a fighter's, so that fluctuations are ve...
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Difficulties concerning the detection of TBMs result from their radial speed, which is higher than a fighter's, and radar cross section (RCS) value, which is lower than a fighter's, so that fluctuations are very complicated. signal processing algorithms relating radar echoes from TBMs in radar with stacked receiving beams are described. Moreover, a simulation model of such echoes is considered. On the basis of these models, introductory research results are presented (see Brenner, T. et al., ibid., p.773-7).
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