Challenges of a complex chip verification come from every aspect, such as network file system (NFS) access, coding style etc. This paper presents some best practices from several sytem-on-chip (SoC) and processor proj...
详细信息
ISBN:
(纸本)9781467368582
Challenges of a complex chip verification come from every aspect, such as network file system (NFS) access, coding style etc. This paper presents some best practices from several sytem-on-chip (SoC) and processor projects we completed recently. It includes: improve NFS access during regression, save and restore technologies for simulation and interactive debug, compilation technologies based on design partitioning and pre-compiled design units, a mixed-signal co-simulation environment involving both UPF based low power RTL simulation and transistor level simulation, etc. These best practices improved the verification productivity and helped us to complete the projects successfully on schedule.
暂无评论