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Fast global motion estimation on single instruction multiple data processors for real-time devices

OPTICAL ENGINEERING 2019年第11期58卷 113105-113105页

作者： Lee, Yun Gu Kwangwoon Univ Sch Software Seoul South Korea

Global motion estimation is a fundamental tool for image processing and computer vision. Since low-cost real-time devices have limited computational resources, the computational burden of global motion estimation remains considerable for low-cost devices. Hence, a fast global motion estimation algorithm for single instruction multiple data (SIMD) processors with which a CPU in modern mobile computing devices is commonly equipped is proposed. Conventional projection-based global motion estimation is modified to improve the prediction accuracy for videos containing large motions. To significantly increase the parallelism, the exact sizes of the variables in each processing step of the proposed algorithm are determined by considering the size of an SIMD register. Simulation results demonstrate that the proposed scheme is considerably fast and accurate, even for videos containing large motions. (C) 2019 Society of Photo-Optical Instrumentation Engineers (SPIE)

关键词： single instruction multiple data parallel processing global motion estimation

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Implanting Machine Learning Accelerator with Multi-Streaming single instruction multiple data Mechanism to RISC-V Processor

Implanting Machine Learning Accelerator with Multi-Streaming...

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Electronic Communications, Internet of Things and Big data (ICEIB), International Conference on

作者： Jih-Ching Chiu Chen-Hao Chao Hao-Yi Chen Jiun-Wen Hsiao Department of Electrical Engineering National Sun Yat-sen University Kaohsiung Taiwan

ISBN: (数字)9798350360721

ISBN: (纸本)9798350360738

We proposed the architecture to accelerate machine learning computation with flexible and diversified features of the convolution-based models. The multi-streaming single instruction multiple data (SIMD) mechanism was built in the proposed accelerator architecture using the RISC-V processor to enhance the smooth instruction flow methods and the high bandwidth data access mechanisms. By analyzing the instruction flow and the data structure, which are needed for machine learning computing in parallelism, we added 87 new instructions for the proposed processor to make the programs of the optimal machine learning algorithms in the SIMD methods. Especially, for balancing the data access latency and the procedure computing time, we applied the locality addressing mode in the buffer space to suit the tiling computing model in famous to solve the machine learning algorithms. After analyzing the five classic convolution neural network models, the average execution speed increased 3.4 times of the ARM Cortex-M55 processor. It is equivalent to the execution speed of the personal computer when the proposed processor operates at 800 MHz frequency.

关键词： Machine learning algorithms Smoothing methods Program processors single instruction multiple data Computational modeling Neural networks Process control

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Mix-GEMM: Extending RISC-V CPUs for Energy-Efficient Mixed-Precision DNN Inference Using Binary Segmentation

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IEEE TRANSACTIONS ON COMPUTERS 2025年第2期74卷 582-596页

作者： Fornt, Jordi Reggiani, Enrico Fontova-Muste, Pau Rodas, Narcis Pappalardo, Alessandro Unsal, Osman Sabri Kestelman, Adrian Cristal Altet, Josep Moll, Francesc Abella, Jaume Barcelona Supercomp Ctr BSC Barcelona 08034 Spain Univ Politecn Catalunya UPC Barcelona 08034 Spain Adv Microdevices AMD Dublin D24 T683 Ireland

Efficiently computing Deep Neural Networks (DNNs) has become a primary challenge in today's computers, especially on devices targeting mobile or edge applications. Recent progress on Post-Training Quantization (PTQ) and Quantization-Aware Training (QAT) has shown that the key to high energy efficiency lies in executing deep learning models with low- (8- to 5-bit) or ultra-low-precision (4- to 2-bit). Unfortunately, current Central Processing Unit (CPU) architectures and instruction Set Architectures (ISAs) present severe limitations on the range of data sizes supported to compute DNN kernels. In this work, we present Mix-GEMM, a hardware-software co-designed architecture that enables RISC-V processors to efficiently compute arbitrary mixed-precision DNN kernels, supporting all data size combinations from 8- to 2-bit. By applying binary segmentation, our architecture can scale its throughput by decreasing the data size of the operands, resulting in a flexible approach capable of leveraging state-of-the-art QAT and PTQ to achieve high energy efficiency at a very low cost. Evaluating our Mix-GEMM architecture in a dual-issue in-order RISC-V processor shows that we are able to boost its performance and energy efficiency by up to 44x and 11x with respect to the baseline processor, with an area overhead of only 2%. This allows our extended processor to execute state-of-the-art DNNs with significantly higher performance and energy efficiency than the standard FP32 precision, while retaining almost the same model accuracy.

关键词： Program processors Computer architecture Energy efficiency Quantization (signal) Artificial neural networks Computers Computational modeling Pipelines Software single instruction multiple data Deep neural networks RISC-V extensions energy efficiency binary segmentation neural accelerators

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PQNTRU: Acceleration of NTRU-Based Schemes via Customized Post-Quantum Processor

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IEEE TRANSACTIONS ON COMPUTERS 2025年第5期74卷 1649-1662页

作者： Ye, Zewen Huang, Junhao Huang, Tianshun Bai, Yudan Li, Jinze Zhang, Hao Li, Guangyan Chen, Donglong Cheung, Ray C. C. Huang, Kejie Zhejiang Univ Coll Informat Sci & Elect Engn Hangzhou 310027 Zhejiang Peoples R China BNU HKBU United Int Coll Zhuhai 519087 Peoples R China City Univ Hong Kong Dept Elect Engn Hong Kong 999077 Peoples R China

Post-quantum cryptography (PQC) has rapidly evolved in response to the emergence of quantum computers, with the US National Institute of Standards and Technology (NIST) selecting four finalist algorithms for PQC standardization in 2022, including the Falcon digital signature scheme. Hawk is currently the only lattice-based candidate in NIST Round 2 additional signatures. Falcon and Hawk are based on the NTRU lattice, offering compact signatures, fast generation, and verification suitable for deployment on resource-constrained Internet-of-Things (IoT) devices. Despite the popularity of ML-DSA and ML-KEM, research on NTRU-based schemes has been limited due to their complex algorithms and operations. Falcon and Hawk's performance remains constrained by the lack of parallel execution in crucial operations like the Number Theoretic Transform (NTT) and Fast Fourier Transform (FFT), with data dependency being a significant bottleneck. This paper enhances NTRU-based schemes Falcon and Hawk through hardware/software co-design on a customized single-instruction-multiple-data (SIMD) processor, proposing new SIMD hardware units and instructions to expedite these schemes along with software optimizations to boost performance. Our NTT optimization includes a novel layer merging technique for SIMD architecture to reduce memory accesses, and the use of modular algorithms (Signed Montgomery and Improved Plantard) targets various modulus data widths to enhance performance. We explore applying layer merging to accelerate fixed-point FFT at the SIMD instruction level and devise a dual-issue parser to streamline assembly code organization to maximize dual-issue utilization. A System-on-chip (SoC) architecture is devised to improve the practical application of the processor in real-world scenarios. Evaluation on 28 $nm$nm technology and field programmable gate array (FPGA) platform shows that our design and optimizations can increase the performance of Hawk signature generation and verif

关键词： single instruction multiple data NIST Internet of Things Polynomials Digital signatures Optimization Computers Computer architecture Lattices Hardware Post-quantum cryptography NTRU falcon hawk RISC-V system-on-chip

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Dyamond: Compact and Efficient 1T1C DRAM IMC Accelerator With Bit Column Addition for Memory-Intensive AI

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2025年第4期60卷 1299-1310页

作者： Hong, Seongyon Jo, Wooyoung Kim, Sangjin Kim, Sangyeob Um, Soyeon Sohn, Kyomin Yoo, Hoi-Jun Korea Adv Inst Sci & Technol KAIST Sch Elect Engn Daejeon 34141 South Korea Samsung Elect FLASH & DRAM Design Team Memory Div Hwaseong 18448 South Korea

This article proposes Dyamond, a one transistor, one capacitor (1T1C) dynamic random access memory (DRAM) in-memory computing (IMC) accelerator with architecture-to-circuit-level optimizations for high memory density and energy efficiency. The bit column addition (BCA) dataflow introduces output bit-wise accumulation to exploit varying accuracy and energy characteristics across different bit positions. The lower BCA (LBCA) reduces analog-to-digital converter (ADC) operations to enhance energy efficiency with inter-column analog accumulation. The higher BCA (HBCA) improves accuracy through signal enhancement and minimizes energy consumption per ADC readout with signal shift (SS). The design maximizes memory density by dedicating 1T1C cells solely to memory and integrating a compact computation circuit adjacent to the bitline sense amplifier. The memory access power is further reduced with a big-little array structure and a switchable sense amplifier (SWSA), which trades off retention time and energy consumption. Fabricated in 28-nm CMOS, Dyamond integrates 3.54-MB DRAM in a 6.48-mm2 area, achieving 27.2 TOPS/W peak efficiency and outstanding performance in advanced models such as BERT and GPT-2.

关键词： Random access memory Energy efficiency Computer architecture Artificial intelligence Arrays single instruction multiple data Computational efficiency System-on-chip In-memory computing Accuracy Artificial intelligence (AI) bit column addition (BCA) dataflow compact MAC-SIMD (CMS) circuit dynamic random access memory (DRAM) in-memory computing (IMC)

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Port Contention Aware Task Scheduling for SIMD Applications

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IEEE ACCESS 2025年 13卷 6204-6216页

作者： Saito, Shogo Fujimoto, Kei NTT Corp Network Innovat Ctr Tokyo 1808585 Japan

single instruction multiple data (SIMD) instructions in central processing units (CPU) are becoming commonly used in usecases such as wireless signal processing and artificial intelligence (AI) inference. When SIMD operations are executed in a simultaneous multi-threading (SMT) environment, a performance degradation event, called port contention, is expected to occur due to the limited number of ports caused by the large size of the SIMD circuit. In this paper, we analyze the occurrence of port contention during SIMD operation and clarify the characteristics that affect the performance of core allocation. On the basis of these performance characteristics, we propose a system that avoids the occurrence of port contention and improves performance. The proposed method features a core allocation policy to avoid port contention, identify SIMD applications, and coordinate with the operating system (OS) scheduler. Through evaluation, we find that the proposed method can reduce the processing time for some tasks in virtual radio access networks was reduced by 13.3%.

关键词： single instruction multiple data Arithmetic instruction sets Resource management Proposals Degradation Decoding Central Processing Unit Microprogramming Load management SIMD load balancing scheduler multi core port contention

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Swift: Fast Secure Neural Network Inference With Fully Homomorphic Encryption

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IEEE TRANSACTIONS ON INFORMATION FORENSICS AND SECURITY 2025年 20卷 2793-2806页

作者： Fu, Yu Tong, Yu Ning, Yijing Xu, Tianshi Li, Meng Lin, Jingqiang Feng, Dengguo Univ Sci & Technol China Sch Cyber Sci & Technol Hefei 230027 Anhui Peoples R China Univ Sci & Technol China Anhui Prov Key Lab Digital Secur Hefei 230027 Anhui Peoples R China Peking Univ Sch Integrated Circuits Beijing 100871 Peoples R China Peking Univ Inst Artificial Intelligence Beijing 100871 Peoples R China Peking Univ Sch Integrated Circuits Beijing 100871 Peoples R China Chinese Acad Sci Inst Software Beijing 100190 Peoples R China

With the widespread use of machine learning (ML), privacy concerns during neural network inference are attracting growing attention. Secure two-party neural network (2PC-NN) inference is the privacy-preserving inference method, which allows client to obtain the inference result without disclosing client's input to the server. The server's model parameters are also confidential to the client. However, current 2PC-NN inference schemes still have large overhead, especially for non-linear functions. In this paper, we present Swift, a fast secure 2PC-NN inference scheme based on fully homomorphic encryption (FHE) and secret sharing (SS). FHE protects the input and model parameters in linear functions, while SS is integrated to protect the non-linear functions. Concretely, Swift integrates FHE and SS to design secure and efficient non-linear protocols used for ReLU and max pooling. To further optimize performance, Swift employs FHE with computation-friendly coefficient encoding for fast execution of linear functions, and SIMD encoding for non-linear functions. Swift constructs efficient encoding conversion protocol between the coefficient-encoded ciphertext and the SIMD-encoded ciphertext. Finally, Swift achieves secure neural network inference framework for MNIST dataset. Compared with Cheetah (USENIX 2022), the execution time of ReLU, max pooling, secure inference under a WAN setting improves 7.4x, 13.3x, 1.9x, respectively.

关键词： Encoding Protocols Neural networks single instruction multiple data Servers Homomorphic encryption Wide area networks Privacy Electronic mail Convolution Neural network inference privacy-preserving inference fully homomorphic encryption

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High-Throughput Software-Defined LDPC Encoder and Decoder With x86-Based data-Level Parallelism

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IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY 2025年第1期74卷 50-60页

作者： Yun, Sangbu Choe, Jeongwon Lee, Youngjoo Pohang Univ Sci & Technol POSTECH Dept Elect Engn Pohang 37673 South Korea

In order to realize the high-throughput software-defined low-density parity-check (SD-LDPC) encoder and decoder for 5G communication systems, this paper presents various algorithm-software co-optimization techniques allowing advanced data-level parallelism. We first develop efficient mapping schemes to describe the contemporary 5G LDPC processing with recent x86 single instruction multiple data (SIMD) instructions. Then, the data rate of 5G SD-LDPC processing is remarkably improved by introducing SIMD-aware algorithm-level innovations, e.g., parallel efficient encoding, minimizing branch instructions, approximate check-node processing, and latency-oriented optimization. Compared with the state-of-the-art approaches, experimental results show that the proposed techniques successfully enhance the speed of encoding and decoding operations by 8.1 and 1.5 times, respectively, leading to the high-speed and fully-flexible software-defined radio (SDR) solutions for 5G systems.

关键词： 5G mobile communication Decoding Encoding single instruction multiple data Iterative decoding Throughput Vectors Error-correction code LDPC decoding 5G new radio SIMD SDR wireless communication

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Batch Inference on Deep Convolutional Neural Networks With Fully Homomorphic Encryption Using Channel-By-Channel Convolutions

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IEEE TRANSACTIONS ON DEPENDABLE AND SECURE COMPUTING 2025年第2期22卷 1674-1685页

作者： Cheon, Jung Hee Kang, Minsik Kim, Taeseong Jung, Junyoung Yeo, Yongdong Seoul Natl Univ Seoul 08826 South Korea CryptoLab Inc Seoul 08826 South Korea

Secure Machine Learning as a Service (MLaaS) is a viable solution where clients seek secure ML computation delegation while protecting sensitive data. We propose an efficient method to securely evaluate deep standard convolutional neural networks based on residue number system variant of Cheon-Kim-Kim-Song (RNS-CKKS) scheme in the manner of batch inference. In particular, we introduce a packing method called Channel-By-Channel Packing that maximizes the slot compactness and single-instruction-multiple-data (SIMD) capabilities in ciphertexts. We also propose a new method for homomorphic convolution evaluation called Channel-By-Channel Convolution, which minimizes the additional heavy operations during convolution layers. Simulation results show that our work has improvements in amortized runtime for inference, with a factor of 5.04 and 5.20 for ResNet-20 and ResNet-110, respectively, compared to the previous results. We note that our results almost simulate the original backbone models, with classification accuracy differing from the backbone within 0.02%p. Furthermore, we show that the client's rotation key size generated and transmitted can be reduced from 105.6 GB to 6.91 GB for ResNet models during an MLaaS scenario. Finally, we show that our method can be combined with previous methods, providing flexibility for selecting batch sizes for inference.

关键词： Convolutional neural networks Vectors Servers Cryptography single instruction multiple data Accuracy Throughput Privacy-preserving machine learning fully homomorphic encryption convolutional neural network ResNet

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A data Prefetcher-Based 1000-Core RISC-V Processor for Efficient Processing of Graph Neural Networks

IEEE COMPUTER ARCHITECTURE LETTERS

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IEEE COMPUTER ARCHITECTURE LETTERS 2025年第1期24卷 73-76页

作者： Khan, Omer Univ Connecticut Elect & Comp Engn Storrs CT 06269 USA

Graphs-based neural networks have seen tremendous adoption to perform complex predictive analytics on massive real-world graphs. The trend in hardware acceleration has identified significant challenges with harnessing graph locality and workload imbalance due to ultra-sparse and irregular matrix computations at a massively parallel scale. State-of-the-art hardware accelerators utilize massive multithreading and asynchronous execution in GPUs to achieve parallel performance at high power consumption. This paper aims to bridge the power-performance gap using the energy efficiency-centric RISC-V ecosystem. A 1000-core RISC-V processor is proposed to unlock massive parallelism in the graphs-based matrix operators to achieve a low-latency data access paradigm in hardware to achieve robust power-performance scaling. Each core implements a single-threaded pipeline with a novel graph-aware data prefetcher at the 1000 cores scale to deliver an average 20x performance per watt advantage over state-of-the-art NVIDIA GPU.

关键词： Prefetching Graphics processing units Sparse matrices Hardware acceleration Vectors single instruction multiple data Multithreading Load modeling Training Social networking (online) Distributed and scalable parallelism graph neural networks graphs sparse and unstructured matrix operators massively parallel hardware

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