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Motion-Based Object Location on a smart image sensor Using On-Pixel Memory

sensorS 2022年第17期22卷 6538页

作者： Valenzuela, Wladimir Saavedra, Antonio Zarkesh-Ha, Payman Figueroa, Miguel Univ Concepcion Fac Engn Dept Elect Engn Concepcion 4070386 Chile Tech Univ Berlin Elect Engn & Comp Sci Fac Inst Comp Engn & Microelect Embedded Syst Architecture Grp D-10623 Berlin Germany Univ New Mexico Sch Engn Dept Elect & Comp Engn ECE Albuquerque NM 87131 USA

Object location is a crucial computer vision method often used as a previous stage to object classification. Object-location algorithms require high computational and memory resources, which poses a difficult challenge for portable and low-power devices, even when the algorithm is implemented using dedicated digital hardware. Moving part of the computation to the imager may reduce the memory requirements of the digital post-processor and exploit the parallelism available in the algorithm. This paper presents the architecture of a smart Imaging sensor (SIS) that performs object location using pixel-level parallelism. The SIS is based on a custom smart pixel, capable of computing frame differences in the analog domain, and a digital coprocessor that performs morphological operations and connected components to determine the bounding boxes of the detected objects. The smart-pixel array implements on-pixel temporal difference computation using analog memories to detect motion between consecutive frames. Our SIS can operate in two modes: (1) as a conventional image sensor and (2) as a smart sensor which delivers a binary image that highlights the pixels in which movement is detected between consecutive frames and the object bounding boxes. In this paper, we present the design of the smart pixel and evaluate its performance using post-parasitic extraction on a 0.35 mu m mixed-signal CMOS process. With a pixel-pitch of 32 mu m x 32 mu mu m, we achieved a fill factor of 28%. To evaluate the scalability of the design, we ported the layout to a 0.18 mu m process, achieving a fill factor of 74%. On an array of 320 x 240 smart pixels, the circuit operates at a maximum frame rate of 3846 frames per second. The digital coprocessor was implemented and validated on a Xilinx Artix-7 XC7A35T field-programmable gate array that runs at 125 MHz, locates objects in a video frame in 0.614 mu s, and has a power consumption of 58 mW.

关键词： smart image sensor smart pixel vision chip intelligent sensor object detection object location motion-based frame difference field-programmable gate array very large scale integration

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Low-power in-pixel buffer circuit for smart image sensor

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sensor REVIEW 2020年第5期40卷 585-590页

作者： Li, Qin Zhu, Huifeng Huang, Guyue Yu, Zijie Qiao, Fei Wei, Qi Liu, Xinjun Yang, Huazhong Tsinghua Univ Dept Elect Engn Beijing Peoples R China Washington Univ Dept Elect & Syst Engn St Louis MO 63110 USA Tsinghua Univ Dept Mech Engn Beijing Peoples R China

Purpose The smart image sensor (SIS) which integrated with both sensor and smart processor has been widely applied in vision-based intelligent perception. In these applications, the linearity of the image sensor is crucial for better processing performance. However, the simple source-follower based readout circuit in the conventional SIS introduces significant nonlinearity. This paper aims to design a low-power in-pixel buffer circuit applied in the high-linearity SIS for the smart perception applications. Design/methodology/approach The linearity of the SIS is improved by eliminating the non-ideal effects of transistors and cancelling dynamic threshold voltage that changes with the process variation, voltage and temperature. A low parasitic capacitance low leakage switch is proposed to further improve the linearity of the buffer. Moreover, an area-efficient SIS architecture with a sharing mechanism is presented to further reduce the number of in-pixel transistors. Findings A low parasitic capacitance low leakage switch and a gate-source voltage pre-storage method are proposed to further improve the linearity of the buffer. Nonlinear effects introduced by parasitic capacitance switching leakage, etc., have been investigated and solved by proposing low-parasitic and low-leakage switches. The linearity is improved without a power-hungry operational amplifier-based calibration circuit and a noticeable power consumption increment. Originality/value The proposed design is implemented using a standard 0.18-mu m CMOS process with the active area of 102 mu m(2). At the power consumption of 5.6 mu W, the measured linearity is -63 dB, which is nearly 27 dB better than conventional active pixel sensor (APS) implementation. The proposed low-power buffer circuit increase not only the performance of the SIS but also the lifetime of the smart perception system.

关键词： Analog buffer High linearity Low power smart image sensor

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Face Recognition on a smart image sensor Using Local Gradients

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sensorS 2021年第9期21卷 2901页

作者： Valenzuela, Wladimir Soto, Javier E. Zarkesh-Ha, Payman Figueroa, Miguel Univ Concepcion Dept Elect Engn Concepcion 4070386 Chile Univ New Mexico Dept Elect & Comp Engn ECE Albuquerque NM 87131 USA

In this paper, we present the architecture of a smart imaging sensor (SIS) for face recognition, based on a custom-design smart pixel capable of computing local spatial gradients in the analog domain, and a digital coprocessor that performs image classification. The SIS uses spatial gradients to compute a lightweight version of local binary patterns (LBP), which we term ringed LBP (RLBP). Our face recognition method, which is based on Ahonen's algorithm, operates in three stages: (1) it extracts local image features using RLBP, (2) it computes a feature vector using RLBP histograms, (3) it projects the vector onto a subspace that maximizes class separation and classifies the image using a nearest neighbor criterion. We designed the smart pixel using the TSMC 0.35 mu m mixed-signal CMOS process, and evaluated its performance using postlayout parasitic extraction. We also designed and implemented the digital coprocessor on a Xilinx XC7Z020 field-programmable gate array. The smart pixel achieves a fill factor of 34% on the 0.35 mu m process and 76% on a 0.18 mu m process with 32 mu m x 32 mu m pixels. The pixel array operates at up to 556 frames per second. The digital coprocessor achieves 96.5% classification accuracy on a database of infrared face images, can classify a 150x80-pixel image in 94 mu s, and consumes 71 mW of power.

关键词： smart image sensor smart pixel vision chip intelligent sensor feature extraction face recognition linear binary patterns linear discriminant analysis field-programmable gate array very large-scale integration

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Neuro Inspired smart image sensor : analog Hmax implementation

Neuro Inspired Smart Image Sensor : analog Hmax implementati...

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Conference on image sensors and Imaging Systems

作者： Paindavoine, Michel Dubois, Jerome Musa, Purnawarman Univ Bourgogne LEAD UMR CNRS 5022 F-21065 Dijon France Univ Picardie Jules Verne INSSET F-02315 St Quentin en Yvelines France Univ Gunadarma Depok West Java Indonesia

ISBN: (纸本)9781628414936

Neuro-Inspired Vision approach, based on models from biology, allows to reduce the computational complexity. One of these models - The Hmax model - shows that the recognition of an object in the visual cortex mobilizes V1, V2 and V4 areas. From the computational point of view, V1 corresponds to the area of the directional filters (for example Sobel filters, Gabor filters or wavelet filters). This information is then processed in the area V2 in order to obtain local maxima. This new information is then sent to an artificial neural network. This neural processing module corresponds to area V4 of the visual cortex and is intended to categorize objects present in the scene. In order to realize autonomous vision systems (consumption of a few milliwatts) with such treatments inside, we studied and realized in 0.35 mu m CMOS technology prototypes of two image sensors in order to achieve the V1 and V2 processing of Hmax model.

关键词： smart image sensor analog implementation Neuro-Inspired Vision

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Attacks on image sensors 22

Attacks on Image Sensors

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IEEE/ACM 41st International Conference on Computer Aided-Design (ICCAD)

作者： Wolf, Marilyn Samal, Kruttidipta Univ Nebraska Lincoln Sch Comp Lincoln NE 68588 USA

ISBN: (纸本)9781450392174

This paper provides a taxonomy of security vulnerabilities of smart image sensor systems. image sensors form an important class of sensors. Many image sensors include computation units that can provide traditional algorithms such as image or video compression along with machine learning tasks such as classification. Some attacks rely on the physics and optics of imaging. Other attacks take advantage of the complex logic and software required to perform imaging systems.

关键词： hardware security image sensor smart image sensor

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Pupil Detection for Augmented and Virtual Reality based on images with Reduced Bit Depths 17

Pupil Detection for Augmented and Virtual Reality based on I...

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17th IEEE sensors Applications Symposium (SAS)

作者： Fiala, Gernot Ye, Zhenyu Steger, Christian Graz Univ Technol Inst Tech Informat Graz Austria Ams OSRAM AG ISS OSS SW Premstaetten Austria

ISBN: (数字)9781665409810

ISBN: (纸本)9781665409810

For future augmented reality (AR) and virtual reality (VR) applications, several different kinds of sensors will be used. These sensors, to give some examples, are used for gesture recognition, head pose tracking and pupil tracking. All these sensors send data to a host platform, where the data must be processed in real-time. This requires high processing power which leads to higher energy consumption. To lower the energy consumption, optimizations of the image processing system are necessary. This paper investigates pupil detection for AR/VR applications based on images with reduced bit depths. It shows that images with reduced bit depths even down to 3 or 2 bits can be used for pupil detection, with almost the same average detection rate. Reduced bit depths of an image reduces the memory foot-print, which allows to perform in-sensor processing for future image sensors and provides the foundation for future in-sensor processing architectures.

关键词： pupil detection smart image sensor augmented reality virtual reality bit depth in-sensor processing

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Bio-inspired smart vision sensor: toward a reconfigurable hardware modeling of the hierarchical processing in the brain

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JOURNAL OF REAL-TIME image PROCESSING 2021年第1期18卷 157-174页

作者： Bhowmik, Pankaj Pantho, Md Jubaer Hossain Bobda, Christophe Univ Florida Dept Elect & Comp Engn Gainesville FL 32611 USA

Biological vision systems inspire processing methods in computer vision applications. This paper employs the insights of vision systems in hardware and presents a pixel-parallel, reconfigurable, and layer-based hierarchical architecture for smart image sensors. The architecture aims to bring computation close to the sensor to achieve high acceleration for different machine vision applications while consuming low power. We logically divide the image into multiple regions and perform pixel-level and region-level processing after removing spatiotemporal redundancy. Those processors use bio-inspired algorithms to activate the regions with region of interest of a scene. The hierarchical processing breaks the traditional sequential image processing and introduces parallelism for machine vision applications. Also, we make the hardware design reconfigurable even after fabrication to make the hardware reusable for different applications. Simulation results show that the area overhead and power penalty for adding reconfigurable features stay in an acceptable range. We emphasize to maximize the operating speed and obtain 800 MHz. Besides, the design saves 84.01% and 96.91% dynamic power at the first and second stages of the hierarchy by removing redundant information. Furthermore, the sequential deployment of high-level reasoning only on the selected regions of the image becomes computationally inexpensive to execute a complex task in real time.

关键词： Biological vision Pixel-level processing Reconfigurability Predictive coding Attention module smart image sensor FPGA ASIC

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Event-Based Re-configurable Hierarchical Processors for smart image sensors 30

Event-Based Re-configurable Hierarchical Processors for Smar...

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30th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP)

作者： Bhowmik, Pankaj Pantho, Jubaer Hossain Bobda, Christophe Univ Florida Dept Elect & Comp Engn Gainesville FL 32611 USA

ISBN: (纸本)9781728116013

This paper presents a reconfigurable hierarchical hardware architecture at the pixel and region level for smart image sensors to accelerate machine vision applications. This architecture maintains hierarchical processing that begins at the pixel level. It reduces the computational burden on the sequential processor and accelerates the overall processing. There are three hierarchical layers, and each layer passes only the relevant information to the next layer by removing redundant information. This method facilitates the final processor to respond if there is an event in the scene. Identifying relevant information is complex, and we adapted different bio-inspired algorithms in the hierarchical layers to meet this purpose. Besides, these processors are made runtime reconfigurable to different applications, and it adds flexibility after fabrication. This hierarchical processing breaks the traditional sequential image processing and introduces parallelism for the machine vision applications. We evaluate the design in FPGA and achieve the GDSII file in ASIC platform at 800MHz. Simulation results show that the area overhead and power penalty for adding reconfiguration feature stay in an acceptable range. Besides, removing redundant information 84.01% and 96.91% dynamic power can be saved at the pixel-level and region-level, respectively.

关键词： Pixel Level Processing Reconfigurability Predictive Coding Attention Module smart image sensor FPGA ASIC

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Distributed mixed-signal architecture for programmable smart image sensors

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ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING 2018年第3期97卷 493-501页

作者： Le Hir, Juliette Kolar, Anthony Dos Santos, Filipe Vinci Sorbonne Univ GeePs Grp Elect Engn Paris CNRSCent SupelecUniv Paris SudUniv Paris Sacla 3&11 Rue Joliot Curie Gif Sur Yvette France Cent Supelec SANA Adv Analog Design Grp 3 Rue Joliot Curie Gif Sur Yvette France

smart vision systems on a chip are promising for embedded applications. Currently, flexibility in the choice of integrated pre-processing tools is obtained at the expense of total silicon area and fill factor, which are otherwise optimized provided that the sensor performs a specific task. We propose a new architecture based on macropixel-level processing to improve the trade-off by using the same processing elements (PEs) for a whole group of pixels. In this paper, we show through transistor-level simulations the feasibility of using macropixel PEs. Their operative part is analog to avoid the bottleneck of analog to digital converters and has digital control which is distributed in and out of the matrix of pixels. PEs are designed to be suitable for coefficient-reconfigurable spatial and temporal filtering. Sharing electronics among several pixels and matching existing algorithms to the target architecture allow for such programmability without degrading too much pixel area nor fill factor.

关键词： smart image sensor Vision system on a chip (VSoC) Focal-plane array Algorithm-architecture matching Mixed analog-digital electronics

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A Streaming Motion Magnification Core for smart image sensors

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2018年第9期65卷 1229-1233页

作者： Shi, Cong Luo, Gang Harvard Med Sch Dept Ophthalmol Schepens Eye Res Inst Massachusetts Eye & Ear Boston MA 02115 USA

This brief proposes a modified Eulerian Video Magnification (EVM) algorithm and a hardware implementation of a motion magnification core for smart image sensors. Compared to the original EVM algorithm, we perform the pixel-wise temporal bandpass filtering only once rather than multiple times on all scale layers, to reduce the memory and multiplier requirement for hardware implementation. A pixel stream processing architecture with pipelined blocks is proposed for the magnification core, enabling it to readily fit common image sensing components with streaming pixel output, while achieving higher performance with lower system cost. We implemented an FPGA-based prototype that is able to process up to 90M pixels per second and magnify subtle motion. The motion magnification results are comparable to the original algorithm running on PC.

关键词： Motion magnification Laplacian pyramid spatiotemporal filtering smart image sensor pixel stream processing

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