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检索条件"主题词=Software Algorithms"

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A first step to the evaluation of SimGrid in the context of a real application

A first step to the evaluation of SimGrid in the context of ...

引用

IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Abdou Guermouche Hélène Renard LaBRI University of Bordeaux 1 Bordeaux France I3S and University Nice/Sophia-Antipolis Sophia-Antipolis France

ISBN: (纸本)9781424465330

Simulation is a ¿simple¿ method to experimentally evaluate the behavior of algorithms designed for parallel and distributed platforms. Moreover, the reliability of the evaluation strongly depends on the models used inside the simulator. This paper is devoted to the study and the evaluation of the behavior of the SimGrid simulator through a comparison between a simulated and a real execution of the same target application (i.e. heat propagation). Our target platforms are heterogeneous and their characteristics may dynamically vary during the execution. The obtained results (on a set of various platforms) show that the behavior observed when using the simulated platform is very close to the one obtained on the real one.

关键词： Computational modeling Distributed computing Application software Peer to peer computing Algorithm design and analysis Large-scale systems Distributed algorithms Resource management Processor scheduling software algorithms

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Proposal of a DH optimization model

Proposal of a DH optimization model

引用

International Conference on Computer, Information and Telecommunication Systems (CITS)

作者： Ahmed El Emine Sejad Khadidiatou Wane Keita Khaly Tall Idy Diop Department of Computer Science ESP / Cheikh Anta Diop University (UCAD) Dakar Senegal Electrical Engineering department ESP / Cheikh Anta Diop University (UCAD) Dakar Senegal

ISBN: (数字)9781728165448

ISBN: (纸本)9781728165455

The Diffie-Hellman (DH) algorithm aims to allow two users who don't know each other before to jointly establish a shared secret key over an insecure communications channel. The DH itself is limited to the exchange of keys and since there is no mechanism which ensures the main security services such as confidentiality, integrity and authentication, the DH algorithm is therefore not immune to "man in the middle" attacks. In this article, we propose a hybrid model called S-SEJAD which combines cryptographic algorithms, DH and AES-128. The S-SEJAD model aims to improve security when exchanging keys with DH algorithm. The results show the effectiveness of strategies applied under the proposed model. Indeed, S-SEJAD outperforms the S-Wane model in time a real improvement over existing solutions such as New-two-Pass, STS and HMQV.

关键词： Encryption Protocols Computational modeling Three-dimensional displays software algorithms Data models Computer science

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An extension to DAG based scheduling for partial dependent tasks An Approach to optimize partial dependent tasks in a distributed system

An extension to DAG based scheduling for partial dependent t...

引用

IEEE India Conference (INDICON)

作者： M.A Shweta Raghavendra Eeratta Sanath.S. Shenoy CTDC INDIA TEC Siemens Technology and Services Pvt. Ltd Bangalore India

Real time applications are now utilizing the computational power of multiprocessor and distributed systems [1] to improve their performance. Usually, these applications solve either data-intensive or compute-intensive problems. Applications executing on distributed systems provide faster response time than running on a stand-alone machine. For an application to execute on a distributed system it has to be decomposable into small and independent tasks, where a task is a single independent unit of execution. These tasks can be distributed to various nodes on a HPC[2] grid or cluster for faster execution. The task allocation to processors on a distributed or multiprocessor system is an NP hard problem [3] and determining an optimal solution has exponential complexity. Some problems cannot be completely decomposable into independent tasks due to the nature of application; this is due to the interdependencies of the tasks. Even if the application is not completely parallelizable, it will execute faster than executing it sequentially, if some of the tasks execute in parallel. As part of this paper, we describe an approach for scheduling tasks on a distributed environment by resolving the partial dependent tasks using the Directed Acyclic Graphs (DAG) [4] and Matrix Manipulation.

关键词： software algorithms Scheduling Program processors Flowcharts Processor scheduling Computer architecture

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Clustering Support for Static Concept Location in Source Code

Clustering Support for Static Concept Location in Source Cod...

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IEEE Workshop on Program Comprehension

作者： Giuseppe Scanniello Andrian Marcus Dipartimento di Matematica e Informatica University of Basilicata Italy Department of Computer Science Wayne State University Detroit USA

One of the most common comprehension activities undertaken by developers is concept location in source code. In the context of software change, concept location means finding locations in source code where changes are to be made in response to a modification request. Static techniques for concept location usually rely on searching the source code using textual information or on navigating the dependencies among software elements. In this paper we propose a novel static concept location technique, which leverages both the textual information present in the code and the structural dependencies between source code elements. The technique employs a textual search in that source code, which is clustered using the Border Flow algorithm, based on combining both structural and textual data. We evaluated the technique against a text search based baseline approach using data on almost 200 changes from five software systems. The results indicate that the new approach outperforms the baseline and that improvements are still possible.

关键词： Clustering algorithms software algorithms software systems Partitioning algorithms Context Engines

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GPU-accelerated WZ factorization with the use of the CUBLAS library

GPU-accelerated WZ factorization with the use of the CUBLAS ...

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Federated Conference on Computer Science and Information Systems (FedCSIS)

作者： Beata Bylina Jarosław Bylina Institute of Mathematics Maria Curie Skĺodowska University Lublin Poland

We present a novel implementation of a dense, square, non-structured matrix factorization algorithm, namely the WZ factorization - with the use of graphics processors (GPUs) and CPUs to gain a high performance at a low cost. We rewrite this factorization as operations on blocks of matrices and vectors. We have implemented our block-vector algorithm on GPUs with the use of an appropriate (and ready-to-use) GPU-accelerated mathematical library, namely the CUBLAS library. We compared the performance of our algorithm with CPU implementations. In particular, our implementation on an NVIDIA Tesla C2050 GPU outperforms a CPU-based implementation. Our results show that the algorithm scales well with the size of matrices; moreover, the larger the matrix, the better the performance. We also discuss the impact of the size of the matrix and the use of ready-to-use mathematical libraries on the numerical accuracy.

关键词： Graphics processing units Libraries Matrix decomposition Vectors Linear systems Computer architecture software algorithms

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Fault location using wavelet packets

Fault location using wavelet packets

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International Conference on Power System Technology (POWERCON)

作者： Feng Yan Zhiye Chen Zhirui Liang Yinghui Kong Peng Li Department of Electric Power Engineering North China Electric Power University Baoding Hebei China

A technique using wavelet packets is presented for accurate fault location on power lines with branches. It relies on detecting fault-generated transient traveling waves and identifies some waves reflected back from discontinuities and the fault point. Wavelet packets analysis is used to decompose and reconstruct high-frequency fault signals. An eigenvector matrix consists of local energies of high-frequency content of the fault signal; the faulty section is determined by comparing local energies in the eigenvector matrix with a given threshold. With the faulty section determined, the time ranges of two reflected waves related with fault point would be found out, then the fault point is located. The paper shows the theoretical development of the algorithm, and together with the results obtained using EMTP simulation software modeling, a simple 10 kV overhead line circuit.

关键词： Fault location Wavelet packets Circuit faults Matrix decomposition Fault detection Fault diagnosis Wavelet analysis Signal analysis software algorithms EMTP

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Computational Experience in Solving Algebraic Riccati Equations

Computational Experience in Solving Algebraic Riccati Equati...

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IEEE Conference on Decision and Control

作者： V. Sima National Institute for Research and Development in Informatics Bucharest Romania

State-of-the-art, uni-processor algebraic Riccati equation solvers for automatic control computations are investigated and compared for various problem sizes. General-purpose SLICOT solvers are very efficient for small-size problems, but they cannot compete for larger problems with specialized solvers designed for certain problem classes, such as Newton solvers using low rank Cholesky factors of the solutions of Lyapunov equations built at each iteration.

关键词： Riccati equations software libraries Optimal control Linear algebra MATLAB software algorithms Biology computing Control system synthesis Biological control systems System analysis and design

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QOS Driven Network-on-Chip Design for Real Time Systems

QOS Driven Network-on-Chip Design for Real Time Systems

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Canadian Conference on Electrical and Computer Engineering (CCECE)

作者： Ankur Agarwal Mehmet Mustafa A. S. Pandya CSE Department FAU Boca Raton FL USA Verizon Laboratories Waltham MA USA

Real time embedded system designers are facing extreme challenges in underlying architectural design selection. It involves the selection of a programmable, concurrent, heterogeneous multiprocessor architecture platform. Such a multiprocessor system on chip (MPSoC) platform has set new innovative trends for the real-time systems and system on chip (SoC) designers. The consequences of this trend imply the shift in concern from computation and sequential algorithms to modeling concurrency, synchronization and communication in every aspect of hardware and software co-design and development. These problems have been addressed by the use of packet switched network on chip (NOC) architecture for future SoCs and thus, real-time systems. Such a NOC based system should be able to support different levels of quality of service (QoS) to meet the real time systems requirements. Thus, it becomes extremely critical to properly design a network interface (NT) and the communication backbone for NOC. In this paper we present a component based design of network interface and communication backbone which supports different levels of QoS. The design has been tested for an adaptive wormhole routing with proactive turn prohibition to guarantee deadlock free on chip communication for NOC architecture. In this work we propose to use the modified turn prohibition (MTP), which has been shown to perform better than up/down and the turn prohibition

关键词： Network-on-a-chip Real time systems Quality of service Computer architecture System-on-a-chip Network interfaces Spine Embedded system Multiprocessing systems software algorithms

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Potential speedup using decimal floating-point hardware

Potential speedup using decimal floating-point hardware

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Asilomar Conference on Signals, Systems & Computers

作者： M.A. Erle M.J. Schulte J.M. Linebarger Electrical & Computer Engr. Lehigh University Bethlehem PA USA Computer Sci. and Engr. Lehigh University Bethlehem PA USA

This paper addresses the potential speedup achieved by using decimal floating-point hardware, instead of software routines, on a high-performance superscalar architecture. software routines were written to perform decimal addition, subtraction, multiplication, and division. Cycle counts were then measured for each instruction using the Simplescalar simulator. After this, new hardware algorithms were developed, existing hardware algorithms were analyzed, and cycle counts were estimated for the same set of instructions using specialized decimal floating-point hardware. This data was then used to show the potential speedup obtained for programs with different instruction mixes and a previously developed benchmark.

关键词： Hardware software algorithms Computer architecture Algorithm design and analysis Costs Computational modeling Floating-point arithmetic Error analysis Manufacturing Velocity measurement

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A comprehensive ASIC/FPGA prototyping environment for exploring embedded processing systems for advanced driver assistance applications

A comprehensive ASIC/FPGA prototyping environment for explor...

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International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS)

作者： Florian Giesemann Guillermo Payá-Vayá Holger Blume Matthias Limmer Werner Ritter Institute of Microelectronic Systems Leibniz Universität Hannover Hannover Germany Vision Enhancement Daimler AG Ulm Germany

The development of complex algorithms for advanced driver assistance systems is a challenging task, due to the high innovation rate and processing demands of applications in this field. The development is usually supported by a software development framework that provides an infrastructure (e.g., access to sensor data) that simulates and evaluates the algorithms. One problem, especially with computationally intensive algorithms, is the slow simulation speed. This paper presents a prototyping environment that connects a software development framework with a FPGA-based hardware platform. This allows implementing computationally intensive tasks in hardware. The proposed rapid prototyping system not only reduces the simulation time, thereby allowing the software designer to evaluate algorithmic parameters with quicker feedback, but also allows verifying and evaluating hardware modules for rapid prototyping. A case study is presented in which a traffic sign detection algorithm is implemented on a soft-core processor. By using the hardware implementation the simulation was accelerated by a factor of 65, compared to the pure software implementation.

关键词： Hardware software software algorithms Field programmable gate arrays Algorithm design and analysis Computational modeling Pins

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