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Analysing software prefetching opportunities in hardware transactional memory

JOURNAL OF SUPERCOMPUTING 2022年第1期78卷 919-944页

作者： Shimchenko, Marina Titos-Gil, Ruben Fernandez-Pascual, Ricardo Acacio, Manuel E. Kaxiras, Stefanos Ros, Alberto Jimborean, Alexandra Uppsala Univ Dept Comp Syst Uppsala Sweden Univ Murcia Comp Engn Dept Murcia Spain

Hardware transactional memory emerged to make parallel programming more accessible. However, the performance pitfall of this technique is squashing speculatively executed instructions and re-executing them in case of aborts, ultimately resorting to serialization in case of repeated conflicts. A significant fraction of aborts occurs due to conflicts (concurrent reads and writes to the same memory location performed by different threads). Our proposal aims to reduce conflict aborts by reducing the window of time during which transactional regions can suffer conflicts. We achieve this by using software prefetching instructions inserted automatically at compile-time. Through these prefetch instructions, we intend to bring the necessary data for each transaction from the main memory to the cache before the transaction itself starts to execute, thus converting the otherwise long latency cache misses into hits during the execution of the transaction. The obtained results show that our approach decreases the number of aborts by 30% on average and improves performance by up to 19% and 10% for two out of the eight evaluated benchmarks. We provide insights into when our technique is beneficial given certain characteristics of the transactional regions, the advantages and disadvantages of our approach, and finally, discuss potential solutions to overcome some of its limitations.

关键词： Hardware transactional memory Parallel programming Compiler software prefetching

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software prefetching for Unstructured Mesh Applications

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ACM TRANSACTIONS ON PARALLEL COMPUTING 2020年第1期7卷 1–23页

作者： Hadade, Ioan Jones, Timothy M. Wang, Feng di Mare, Luca Univ Oxford Oxford Thermofluids Inst Oxford England Univ Cambridge Comp Lab Cambridge England

This article demonstrates the utility and implementation of software prefetching in an unstructured finite volume computational fluid dynamics code of representative size and complexity to an industrial application and across a number of modern processors. We present the benefits of auto-tuning for finding the optimal prefetch distance values across different computational kernels and architectures and demonstrate the importance of choosing the right prefetch destination across the available cache levels for best performance. We discuss the impact of the data layout on the number of prefetch instructions required in kernels with indirect addressing patterns and show how to best implement them in an existing large-scale computational fluid dynamics application. Through this, we show significant full application speed-ups on a range of processors and realistic test cases in both single core/tile and full socket configurations, such as 1.14x on the Intel Xeon Sandy Bridge, 1.09x on the Intel Xeon Broadwell, 1.29x on the Intel Xeon Skylake, 1.99x on the in-order Intel Xeon Phi Knights Corner coprocessor, and 1.51x on the out-of-order Intel Xeon Phi Knights Landing many-core processor.

关键词： software prefetching unstructured mesh irregular memory access auto-tuning performance optimisation

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APT-GET: Profile-Guided Timely software prefetching 22

APT-GET: Profile-Guided Timely Software Prefetching

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17th European Conference on Computer Systems (EuroSys)

作者： Jamilan, Saba Khan, Tanvir Ahmed Ayers, Grant Kasikci, Buis Litz, Heiner Univ Calif Santa Cruz Santa Cruz CA 95064 USA Univ Michigan Ann Arbor MI 48109 USA Google New York NY USA

ISBN: (纸本)9781450391627

prefetching which predicts future memory accesses and preloads them from main memory, is a widely-adopted technique to overcome the processor-memory performance gap. Unfortunately, hardware prefetchers implemented in today's processors cannot identify complex and irregular memory access patterns exhibited by modern data-driven applications and hence developers need to rely on software prefetching techniques. We investigate the challenges of enabling effective, automated software data prefetching. Our investigation reveals that the state-of-the-art compiler-based prefetching mechanism falls short in achieving high performance due to its static nature. Based on this insight, we design APT-GET, a novel profile-guided technique that ensures prefetch timeliness by leveraging dynamic execution time information. APT-GET leverages efficient hardware support such as Intel's Last Branch Record (LBR), for collecting application execution profiles with negligible overhead to characterize the execution time of loads. APT-GET then introduces a novel analytical model to find the optimal prefetch-distance and prefetch injection site based on the collected profile to enable timely prefetches. We study APT-GET in the context of 10 real-world applications and demonstrate that it achieves a speedup of up to 1.98x and of 1.30x on average. By ensuring prefetch timeliness, APT-GET improves the performance by 1.25x over the state-of-the-art software data prefetching mechanism.

关键词： software prefetching Compiler Analysis

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Energy Optimization by software prefetching for Task Granularity in GPU-Based Embedded Systems

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 2020年第6期67卷 5120-5131页

作者： Wang, Zhuowei Cheng, Lianglun Wang, Hao Zhao, Wuqing Song, Xiaoyu Guangdong Univ Technol Sch Comp Guangzhou 510006 Peoples R China Wuhan Donghu Univ Sch Comp Sci Wuhan 430074 Peoples R China Norwegian Univ Sci & Technol Dept Comp Sci N-7491 Trondheim Norway CSG Digital Power Grid Res Inst Co Ltd Guangzhou 510000 Peoples R China Portland State Univ Dept Elect & Comp Engn Portland OR 97207 USA

Energy saving and optimization play an increasingly important role in industrial electronic systems. A heterogeneous embedded system is composed of a general-purpose central processing unit with an enhanced module of graphics processing units (GPU). This article explores the effective strategies of task granularity and software prefetching for energy optimization. In this article, we propose a novel energy optimization model for GPU-based embedded systems by harnessing a communication-based pipeline spatial and temporal relation. We analyze the characteristics of a multiple thread execution of parallel GPUs. We present an effective algorithm for the dynamic power optimization with the adaptively adjusted distance of software prefetching. The experimental results show that the dynamic energy consumption can be saved by 22.1% and 21.8%, respectively, under two prefetching strategies (register and shared memory) without loss of performance. We demonstrate the effectiveness of the proposed methods for energy saving and consumption reduction of performance driven computing in industrial scenarios.

关键词： Communication-computing pipeline spatio-temporal diagram heterogeneous embedded systems low power optimization software prefetching task partition

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software prefetching for Indirect Memory Accesses: A Microarchitectural Perspective

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ACM TRANSACTIONS ON COMPUTER SYSTEMS 2019年第3期36卷 8-8页

作者： Ainsworth, Sam Jones, Timothy M. Univ Cambridge Cambridge England Dept Comp Sci & Technol William Gates Bldg15 JJ Thomson Ave Cambridge CB3 0FD England

Many modern data processing and HPC workloads are heavily memory-latency bound. A tempting proposition to solve this is software prefetching, where special non-blocking loads are used to bring data into the cache hierarchy just before being required. However, these are difficult to insert to effectively improve performance, and techniques fir automatic insertion are currently limited. This article develops a novel compiler pass to automatically generate software prefetches for indirect memory accesses, a special class of irregular memory accesses often seen in high-performance workloads. We evaluate this across a wide set of systems, all of which gain benefit from the technique. We then evaluate the extent to which good prefetch instructions are architecture dependent and the class of programs that are particularly amenable. Across a set of memory-bound benchmarks, our automated pass achieves average speedups of 1.3x for an Intel Haswell processor, 1.1x for both an ARM Cortex-A57 and Qualcomm Kryo, 1.2x for a Cortex-72 and an Intel Kaby Lake, and 1.35x for an Intel Xeon Phi Knight's Landing, each of which is an out-of-order core, and performance improvements of 2.1x and 2.7x for the in-order ARM Cortex -A53 and first generation Intel Xeon Phi.

关键词： software prefetching Compiler Analysis Microarchitecture

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software prefetching for unstructured mesh applications 8

Software prefetching for unstructured mesh applications

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8th IEEE/ACM Workshop on Irregular Applications: Architectures and Algorithms (IA3)

作者： Hadade, Ioan Jones, Timothy M. Wang, Feng di Mare, Luca Univ Oxford Oxford Thermofluids Inst Oxford England Univ Cambridge Comp Lab Cambridge England

ISBN: (纸本)9781728101866

Applications that exhibit regular memory access patterns usually benefit transparently from hardware prefetchers that bring data into the fast on-chip cache just before it is required, thereby avoiding expensive cache misses. Unfortunately, unstructured mesh applications contain irregular access patterns that are often more difficult to identify in hardware. An alternative for such workloads is software prefetching, where special non-blocking instructions load data into the cache hierarchy. However, there are currently few examples in the literature on how to incorporate such software prefetches into existing applications with positive results. This paper addresses these issues by demonstrating the utility and implementation of software prefetching in an unstructured finite volume CFD code of representative size and complexity to an industrial application and across a number of processors. We present the benefits of auto-tuning for finding the optimal prefetch distance values across different computational kernels and architectures and demonstrate the importance of choosing the right prefetch destination across the available cache levels for best performance. We discuss the impact of the data layout on the number of prefetch instructions required in kernels with indirect-access patterns and show how to integrate them on top of existing optimisations such as vectorisation. Through this we show significant full application speed-ups on a range of processors, such as the Intel Xeon Skylake CPU (15%) as well as on the in-order Intel Xeon Phi Knights Corner (1.99 x) architecture and the out-of-order Knights Landing (33%) manycore processor.

关键词： software prefetching unstructured mesh computational fluid dynamics irregular memory access memory parallelism auto-tuning

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ESPN: Memory-Efficient Multi-vector Information Retrieval 23

ESPN: Memory-Efficient Multi-vector Information Retrieval

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23rd ACM SIGPLAN International Symposium on Memory Management (ISMM)

作者： Shrestha, Susav Reddy, Narasimha Li, Zongwang Texas A&M Univ College Stn TX 77843 USA Samsung Semicond San Jose CA USA

ISBN: (纸本)9798400706158

Recent advances in large language models have demonstrated remarkable effectiveness in information retrieval (IR) tasks. While many neural IR systems encode queries and documents into single-vector representations, multi-vector models elevate the retrieval quality by producing multi-vector representations and facilitating similarity searches at the granularity of individual tokens. However, these models significantly amplify memory requirements for retrieval indices by an order of magnitude. This escalation in index size renders the scalability of multi-vector IR models progressively challenging due to their substantial memory demands. We introduce Embedding from Storage Pipelined Network (ESPN) where we offload the entire re-ranking embedding tables to SSDs and reduce the memory requirements by 5 - 16x. We design a flexible software prefetcher applicable to any hierarchical clustering based search, achieving hit rates exceeding 90%. ESPN improves SSD based retrieval up to 6.4x and end-to-end throughput by 68% to maintain near-memory levels of query latency even for large query batch sizes. The code is available at https://***/susavlsh10/ESPN-v1.

关键词： Multi-vector Neural Information Retrieval Memory & Storage System software prefetching Approximate Nearest Neighbor Search GPUDirect Storage

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software Pre-execution for Irregular Memory Accesses in the HBM Era 2022

Software Pre-execution for Irregular Memory Accesses in the ...

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31st ACM SIGPLAN International Conference on Compiler Construction (CC)

作者： Mehta, Sanyam Elsesser, Gary Greyzck, Terry HPE Bloomington MN 55435 USA

ISBN: (纸本)9781450391832

The introduction of High Bandwidth Memory (HBM) necessitates the use of intelligent software prefetching in irregular applications to utilize the surplus bandwidth. In this work, we propose software Pre-execution (SPE), a technique that relies on pre-executing a minimal copy of the loop of concern (we call the pre-execution loop) for the purpose of prefetching irregular accesses. This is complemented by the compiler's enforcing a certain prefetch distance through apriori strip-mining of the original loop such that the execution of the pre-execution loop is interspersed with the main loop to ensure timeliness of prefetches. We find that this approach provides natural advantages over prior art such as preservation of loop vectorization, handling short loops, avoiding performance bottlenecks, amenability to threading and most importantly, effective coverage. We demonstrate these advantages using a variety of benchmarks on Fujitsu's A64FX processor with HBM2 memory - we outperform prior art by 1.3x and 1.2x when using small and huge pages, respectively. Simulations further show that our approach holds stronger promise on upcoming processors with HBM2e.

关键词： software prefetching Pre-execution HBM Graph applications Irregular memory access

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Optimum prefetching Patterns Searching: A Case Study of Matrix-Matrix Multiplication 37

Optimum Prefetching Patterns Searching: A Case Study of Matr...

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37th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)

作者： Khomongkonudom, Varintom Chaikarn, Panyayot Prince Songkla Univ Dept Comp Engn Hat Yai Thailand

ISBN: (数字)9781665485593

ISBN: (纸本)9781665485593

prefetching reduces data fetch latency and augments the speed of program execution. This paper presents an analysis model for selecting the optimum prefetching pattern for matrix-matrix multiplication. By calculating the number of prefetch instructions and the amount of data from prefetching, numbers of prefetching candidates are selected. Then the best prefetching pattern is obtained by selecting the candidate with lowest value of memory access. The prefetching pattern obtained from this algorithm is on average 18.86 percent faster than without prefetching. It is on average 17.54 percent faster than the automatic prefetching feature provided by the Intel C compiler.

关键词： software prefetching matrix-matrix multiplications memory access algorithm

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Modelling the Earth's geomagnetic environment on Cray machines using PETSc and SLEPc

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CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2020年第20期32卷 e5660-e5660页

作者： Brown, Nick Bainbridge, Brian Beggan, Ciaran Brown, William Hamilton, Brian Macmillan, Susan Univ Edinburgh Bayes Ctr EPCC Edinburgh EH8 9BT Midlothian Scotland British Geol Survey Lyell Ctr Edinburgh Midlothian Scotland

The British Geological Survey's global geomagnetic model, Model of the Earth's Magnetic Environment (MEME), is an important tool for calculating the strength and direction of the Earth's magnetic field, which is continually in flux. While the ability to collect data from ground-based observation sites and satellites has grown rapidly, the memory bound nature of the original code has proved a significant limitation on the size of the modelling problem required. In this paper, we describe work done replacing the bespoke, sequential, eigensolver with that of the PETSc/SLEPc package for solving the system of normal equations. Adopting PETSc/SLEPc also required fundamental changes in how we built and distributed the data structures, and as such, we describe an approach for building symmetric matrices that provides good load balance and avoids the need for close coordination between the processes or replication of work. We also study the memory bound nature of the code from an irregular memory accesses perspective and combine detailed profiling with software cache prefetching to significantly optimise this. Performance and scaling characteristics are explored on ARCHER, a Cray XC30, where we achieved a speed up for the solver of 294 times by replacing the model's bespoke approach with SLEPc.

关键词： HPC Model of the Earth's Magnetic Environment (MEME) MPI parallel programming PETSc SLEPc software prefetching

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