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RTHS: A Low-Cost High-Performance Real-Time Hardware Sorter, Using a Multidimensional sorting algorithm

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2019年第7期27卷 1601-1613页

作者： Norollah, Amin Derafshi, Danesh Beitollahi, Hakem Fazeli, Mahdi Iran Univ Sci & Technol Dept Comp Engn Tehran *** Iran

This paper proposes a novel hardware-based multi-dimensional sorting algorithm and its respective architecture, called real-time hardware sorter (RTHS), for emerging data intensive processing applications where performance and resource conservation are serious concerns. The basic idea behind RTHS is to reduce the hardware complexity of parallel hardware sorting architectures (PHSAs) through a high-performance scalable matrix-based sorting method. The proposed method can also be used for implementing Min/Max queues or finding the largest/smallest records exclusively in the big data application. Implementing the RTHS design on a Virtex-7 field-programmable gate array (FPGA) reveals that the number of lookup tables (LUTs) of the proposed method has decreased by 66.3% and 87.3% compared to the conventional Bitonic sorting network (CBSN) and the state-of-the-art PHSA, respectively. In addition, the number of required registers for the proposed method has decreased by 94.8% compared to the state-of-the-art PHSA.

关键词： Bitonic sorting network field-programmable gate array (FPGA) hardware accelerator low-cost design parallel sorting real-time sorter sorting algorithm sorting network

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A Optimized Capacitor Voltage Balance Strategy using Binary Number sorting algorithm for Modular Multilevel Converter 8

A Optimized Capacitor Voltage Balance Strategy using Binary ...

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8th IEEE International Symposium on Next-Generation Electronics (ISNE)

作者： Wang, Donghao Zhang, Baoge Lanzhou Jiaotong Univ Dept Automat & Elect Engn Lanzhou Peoples R China

ISBN: (纸本)9781728120621

Capacitor voltage balancing strategy for Suhmodules (SMs) is one of the key technologies for modular multi-level converters(MMC). The conventional strategy has the problems of large computation and high switching frequency of devices. In order to solve these problems, a mark and operation voltage balancing strategy (MOVBS) is proposed. This strategy marks SMs with two different labels according to the amplitude of capacitor voltage of SMs and current direction of arms, then do sorting and selecting operations to SMs based on the marking results. It reduces sorting times, switching frequency and power loss of devices. For capacitor voltage sorting process, a binary radix sorting algorithm(BRSA) is proposed to improve sorting speed and efficiency of MOVBS. Finally, the feasibility and effectiveness of the MOVBS is verified with a 11-level MMC-HVDC simulation model created in Matlab/Simulink.

关键词： modular multilevel converters capacitor voltage balancing switching frequency power loss sorting algorithm

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The Impact of Execution Frequency in sorting algorithm on Nearest Level Modulated Modular Multilevel Converter 10

The Impact of Execution Frequency in Sorting Algorithm on Ne...

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IEEE 10th International Symposium on Power Electronics for Distributed Generation Systems (PEDG)

作者： Niu, Jiahao Wang, Fred Univ Tennessee Min H Kao Dept Elect Engn & Comp Sci Knoxville TN 37996 USA Oak Ridge Natl Lab Knoxville TN USA

ISBN: (纸本)9781728124551

sorting algorithm is required for operating modular multilevel converter (MMC) with nearest level modulation, to keep the unbalanced submodule capacitor voltage within an acceptable range. Several sorting algorithms have been proposed in previous literatures. However, very few papers discussed about how to select the execution frequency of a sorting algorithm. This paper aims to investigate on the impact of the execution frequency in sorting algorithm on the output voltage harmonics, average switching frequency, submodule capacitor voltage fluctuation of an MMC using nearest level modulation. Multiple MMC models with different number of submodules are built in MATLAB/Simulink. Three different types of sorting algorithms are implemented, and evaluated at various execution frequencies as well as different operating points. Conclusions drawn from the extensive simulations show that to select a sorting algorithm and its execution frequency, all three performance criterions should be considered simultaneous and a minimum execution frequency is always required.

关键词： Modular Multilevel Converter sorting algorithm Execution Frequency

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Modified capacitor voltage balancing sorting algorithm for modular multilevel converter

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JOURNAL OF ENGINEERING-JOE 2019年第16期2019卷 3315-3319页

作者： Zhang, Jie Liu, Jun Liu, Jiayu Fang, Wanliang Hou, Junxian Dong, Yifeng Xi An Jiao Tong Univ Shaanxi Key Lab Smart Grid Xian 710049 Shaanxi Peoples R China China Elect Power Res Inst Beijing 100085 Peoples R China

The modular multilevel converter (MMC) with large-scale sub-modules has the advantage of simpler modulation, lower switching frequency, and lower harmonic component, thus would be very promising in voltage source converter (VSC)-high voltage direct current transmission systems. Conventional capacitor voltage balancing algorithm suffers from insufficient grouping and sorting techniques. Therefore, it might result in excessive computation and high switching frequency of power electronic devices. To address the problem, a modified capacitor voltage balancing sorting algorithm is proposed in this paper. The proposed algorithm could avoid sorting all the module capacitor voltages by selecting only a certain number of the largest or smallest module capacitor voltages, and thus reduces time complexity greatly without losing control precision. Furthermore, the proposed algorithm focuses on the sub-modules whose capacitor voltage exceeds the limits, while the switching states of the other sub-modules are maintained to some degrees by employing the maintaining factor. Therefore, the switching frequency of the power electronic devices is further reduced. The performance of the proposed algorithm is evaluated through a time-domain MMC-HVDC simulation in PSCAD/EMTDC. Results show that the proposed algorithm is able to balance the module voltage with lower computation and reduce the switching frequency of power devices significantly, without noticeably increasing the capacitor voltage ripples.

关键词： HVDC power convertors power grids HVDC power transmission power transmission control computational complexity PWM power convertors capacitors voltage control power electronics electric current control power capacitors power convertors sorting power system simulation modified capacitor voltage sorting algorithm modular multilevel converter large-scale sub-modules simpler modulation lower switching frequency lower harmonic component VSC-high voltage direct current transmission systems sorting techniques high switching frequency power electronic devices largest capacitor voltages smallest module capacitor voltages switching states module voltage capacitor voltage ripples PSCAD EMTDC time-domain MMC-HVDC simulation

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Super Sort sorting algorithm 3

Super Sort Sorting Algorithm

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3rd International Conference for Convergence in Technology (I2CT)

作者： Gugale, Yash PES Modern Coll Engn Dept Comp Engn Pune Maharashtra India

ISBN: (纸本)9781538642733

sorting algorithms are a major area of research in computer science and engineering where the simple task of sorting the numbers leads to complex algorithms. In recent years, many researchers have proposed several sorting techniques to enhance time and space complexities of the algorithms. The sorting technique presented in this paper makes use of the natural sequence of sorted elements in an array of random numbers so as to reduce the number of steps needed to sort. The complexity of the proposed algorithm is O(nlogn) where n represents the number of elements in the input array.

关键词： sorting algorithm super sort time complexity space complexity

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MONTRES-NVM: an External sorting algorithm for Hybrid Memory 7

MONTRES-NVM: an External Sorting Algorithm for Hybrid Memory

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7th IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA)

作者： Khernache, Mohammed Bey Ahmed Laga, Arezki Boukhobza, Jalil Univ Bretagne Sud Lab STICC UMR 6285 F-56100 Lorient France Univ Bretagne Occidentale Lab STICC UMR 6285 F-29200 Brest France

ISBN: (纸本)9781538674031

DRAM technology is approaching its scaling limit and the use of emerging NVM is seen as one possible solution to such an issue. As NVM technologies are not mature enough and does not outperform DRAMs, several studies expect the use of hybrid main memories containing both DRAM and PCM NVM. Redesigning applications for such systems is mandatory as PCM does not have the same performance model as DRAM. In this context, we designed a hybrid memory-aware sorting algorithm called MONTRES-NVM. Since an NVM-based hybrid memory presents a performance gap between DRAM and PCM, we believe that the sorting algorithm falls in the external sorting category. As a matter of fact, we extended our previously designed flash-based external sorting algorithm MONTRES for a hybrid memory by taking profit of byte addressability, and performance asymmetry between reads and writes. MONTRES-NVM enhances the performance of the merge sort algorithm on PCM by more than 60%, the merge sort on DRAM by 3-40% and MONTRES (on a hybrid memory) by 3-33% according to the proportion of already sorted data in the dataset.

关键词： sorting algorithm Hybrid memory Non Volatile Memory Phase Change Memory

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Novel Hash-Based Radix sorting algorithm

Novel Hash-Based Radix Sorting Algorithm

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IEEE Annual Ubiquitous Computing, Electronics & Mobile Communication Conference (UEMCON)

作者： Paul K. Mandal Abhishek Verma California State University Fullerton Fullerton USA New Jersey City University Jersey City NJ

ISBN: (纸本)9781728138862

sorting remains a quintessential problem in computer science; henceforth, considerable research has focused on optimizing runtime efficiency when sorting a collection of elements. Most algorithms for sorting objects are comparison-based. Bucket Sort and Radix Sort are non-comparison based sorting algorithms that can sort objects in linear time. In both cases, the corresponding array indices represent a hash for the object. Nevertheless, Radix Sort still requires an auxiliary array. In this paper, replacing Radix Sort's auxiliary array with a hash table is proposed. Use of a hash table in Radix Sort should avoid the calculations for the array and be better suited for handling objects. As with an array-based Radix sort, this hash-based approach should maintain linearity, thereby sorting objects more efficiently. Following successfully programming this novel sorting algorithm, as the number of elements increases, the runtime progresses linearly, not exponentially. Moreover, as the number of digits increases, the sorting runtime still lengthens linearly. Thus, a hash-based Radix sort is feasible and overcomes many issues associated with current sorting algorithms.

关键词： file organisation sorting radix sorting file organisation sorting programs Hash table grade sorting algorithm Runtime

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Research And Implementation of Database High Performance sorting algorithm With Big Data 2

Research And Implementation of Database High Performance Sor...

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2017 IEEE 2nd International Conference on Big Data Analysis（ICBDA 2017）

作者： Chen Hongyan Wan Junwei Lu Xianli Beijing Institute of Tracking and Telecommunicaitons Technology

ISBN: (纸本)9781509036202

According to the demand of large data sorting algorithm,a new efficient algorithm for large data sorting is *** algorithm by constructing the equivalent sort keys,optimized quicksort algorithm;through the technology of task driven,AIO and double buffer mechanism to make full use of system resources;in algorithm implementation,using multi thread processing tasks,by controlling the number of threads of control *** utilization of these technologies,the algorithm will achieve the separation of database connections and threads,and improve the concurrency of database support,so that the ranking of big data performance close to the theoretical limit value.

关键词： domestic database Big data sorting algorithm Independently controllable Equivalent sort keys

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ImageRank: A Novel sorting algorithm with Relevance Feedback in Application of National Costume Image Retrieval 2

ImageRank: A Novel Sorting Algorithm with Relevance Feedback...

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2nd IEEE International Conference on Signal and Image Processing (ICSIP)

作者： Ma, Baiyou Xu, Tianwei Zhou, Juxiang Yunnan Normal Univ Key Lab Educ Informatizat Nationalities Minist Educ Kunming Yunnan Peoples R China Jining Med Univ Acad Affairs Off Jining Peoples R China

ISBN: (纸本)9781538609699

It is difficult to obtain fairly satisfactory result for national costume images retrieval in real application using existing search engine due to the complexity of visual features and semantic information implied in national costume. Given the fact, a novel sorting algorithm ImageRank is proposed for image retrieval with relevance feedback in this paper, inspired by the PageRank algorithm used by Google Search to rank websites or webpages in their search engine results. ImageRank is realized based on Lucene Image Retrieval (LIRE) toolkit, which is a Java library that provides a simple way to retrieve images and photos based on color and texture characteristics. And it assimilates a good deal of PageRank to accomplish efficient image retrieval by ensuring accurate level of images correlation in resource repository through update the indexical (points-to) relationship timely according to user's behavior dynamically. Experimental results investigate that the performance of ImageRank is better than LIRE. In addition, the conservativeness and convergence of IR value in ImageRank are also verified.

关键词： image retrieval relevance feedback LIRE sorting algorithm national costume

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Implementation of Highly Efficient sorting algorithm for Median Filtering using FPGA Spartan 6

Implementation of Highly Efficient Sorting Algorithm for Med...

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IEEE International Conference on Innovative Mechanisms for Industry Applications (ICIMIA

作者： Korakoppa, Vidya P. Mohana Aradhya, H. V. Ravish RV Coll Engn Dept Telecommun Engn Bangalore Karnataka India RV Coll Engn Dept Elect & Commun Engn Bangalore Karnataka India

ISBN: (纸本)9781509059607

Reducing the noise content in an image is the important factor in image processing and its applications. Some of the noises which cause a serious degradation in the image quality are multiplicative noise, salt and pepper noise, impulse noise, gaussian noise, additive noise etc. Among these, salt and pepper noise can be eliminated using median filtering techniques. sorting techniques have been beneficial for median filtering. In this paper a highly efficient optimized sorting algorithm is implemented for median filter. Median filter is used to calculate the median of set of pixel values of a window. To compare the same column pixel values, data is acquired from FPGA parallely. The adjacent median filter results are saved temporarily using D flip-flops. This method increases the efficiency of execution by reducing the comparisons from 21 to 13 and significantly increases 40% efficiency. sorting algorithm is implemented using FPGA Spartan 6 LX45. It is cost efficient and also power efficient since it consumes half the power compared to earlier Spartan families.

关键词： image processing salt and pepper noise median filter sorting algorithm moving window

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