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SpecBoost: Accelerating Tiled sparse matrix multiplication via Dataflow Speculation

IEEE ACCESS 2025年 13卷 45568-45576页

作者： Seo, Gwanghwi Ryu, Sungju Sogang Univ Dept Elect Engn Seoul 100611 South Korea Sogang Univ Dept Syst Semicond Engn Seoul 04107 South Korea

sparse matrix-sparse matrix multiplication (SpMSpM) is crucial in many fields such asscientific computing, sparse linear algebra, and machine learning due to its computational complexity inthe large and extremely sparse datasets. Various applications dealing with the sparse matrix show a varietyof sparse matrix patterns, so the inner product, outer product, and Gustavson (row-wise) methods havebeen selectively used for the acceleration of the sparse matrix computation. Previous works determine afixed dataflow before the computation. However, such an approach cannot optimize all the input matricetypes having various data patterns. To address these limitations, we propose a SpecBoost, a method thatdynamically selects an optimal tile-level SpMSpM dataflow by analyzing the sparsity pattern within eachmatrix tile and speculating the best tiled dataflow scheme before the computational stage. We compared ourmethod with the widely known previous methods (CSSpa, ExTensor, MatRaptor), and experimental resultsshow that on average our method reduced memory accesses by a factor of (4.01x, 2.86x, 2.22x) and booststhe performance of prior works over the baseline by (4.62x, 2.40x, 1.59x).

关键词： sparse matrices Indexes IP networks Machine learning Computational efficiency Vectors Reviews Quantization (signal) Merging Memory management matrix tiling sparse matrix multiplication tile-level dataflow speculator matrix sampling with threshold

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GAS: General-Purpose In-Memory-Computing Accelerator for sparse matrix multiplication

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IEEE TRANSACTIONS ON COMPUTERS 2024年第6期73卷 1427-1441页

作者： Zhang, Xiaoyu Li, Zerun Liu, Rui Chen, Xiaoming Han, Yinhe Chinese Acad Sci Inst Comp Technol Beijing 100190 Peoples R China Univ Chinese Acad Sci Beijing 100190 Peoples R China Xiangtan Univ Sch Mat Sci & Engn Xiangtan 411105 Hunan Peoples R China

sparse matrix multiplication is widely used in various practical applications. Different accelerators have been proposed to speed up sparse matrix-dense vector multiplication (SpMV), sparse matrix-sparse vector multiplication (SpMSpV), sparse matrix-dense matrix multiplication (SpMM), and sparse matrix-sparse matrix multiplication (SpMSpM). The performance of traditional sparse matrix multiplication accelerators is typically bounded by memory access due to the poor data locality and irregular memory access. In-memory computing (IMC) is a promising technique to alleviate the memory bottleneck. Previous IMC studies are mostly focused on accelerating a single sparse matrix multiplication function. In this paper, we propose GAS, a general-purpose IMC accelerator for sparse matrix multiplication. GAS integrates non-volatile memory based content-addressable memory (CAM) arrays and multiply-add computation (MAC) arrays to support sparse matrices represented in the double-precision floating-point format. Using a unified outer product based multiplication methodology, GAS supports the acceleration of SpMV, SpMSpv, SpMM, and SpMSpM. We further propose four optimization techniques to speed up the computation of GAS. GAS achieves significant speedups and energy savings over central processing unit (CPU) and graphics processing unit (GPU) implementations. Compared with state-of-the-art traditional and IMC-based accelerators, GAS not only supports more functions, but also achieves higher performance and energy efficiency.

关键词： sparse matrices FeFETs Computer architecture Arrays Nonvolatile memory Microprocessors Vectors sparse matrix multiplication in-memory computing SpMV SpMSpV SpMM SpMSpM

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A Context-Awareness and Hardware-Friendly sparse matrix multiplication Kernel for CNN Inference Acceleration

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IEEE TRANSACTIONS ON COMPUTERS 2025年第4期74卷 1182-1195页

作者： Wang, Haotian Ding, Yan Liu, Yumeng Liu, Weichen Liu, Chubo Yang, Wangdong Li, Kenli Hunan Univ Coll Informat Sci & Engn Changsha 410082 Peoples R China Natl Supercomp Ctr Changsha Changsha 410082 Peoples R China Hunan Univ Coll Comp Sci & Elect Engn Changsha 410082 Peoples R China Xiangjiang Lab Changsha 410205 Peoples R China Chinese Acad Sci Inst Software Beijing 100190 Peoples R China Nanyang Technol Univ Coll Comp Sci & Engn Singapore 639798 Singapore

Sparsification technology is crucial for deploying convolutional neural networks in resource-constrained environments. However, the efficiency of sparse models is hampered by irregular memory access patterns in sparse matrix multiplication kernels. Hardware-level support for 2:4 granularity in sparse tensor cores presents an opportunity for designing efficient sparse matrix multiplication kernels. Existing approaches often involve adjusting sparse structures or secondary sparsification, introducing additional computational errors. To tackle this challenge, we introduce a flexible 2:4 structured adaptive sparse matrix multiplication (FS-AMM) method, a hardware-friendly sparse matrix multiplication kernel that leverages model context to accelerate convolutional neural networks. First, we propose a model context-aware matrix pre-processing method that employs heuristic algorithms to estimate a loss of accuracy due to weight sparsity at each layer. Second, we design a hardware-friendly sparse storage format that combines 2:4 sparse and dense storage formats, enabling more versatile sparsity ratio selection. Third, we implement efficient matrix multiplication kernels to optimize GPU utilization. Finally, experimental results on A100 GPUs show that our method effectively utilizes the sparse tensor kernel and obtains an average 3.09 times speedup ratio compared to other sparse methods while maintaining a high accuracy.

关键词： sparse matrices Computational modeling Tensors Kernel Accuracy Graphics processing units Convolutional neural networks Hardware Convolution Adaptation models 2:4 sparsity CNNs filter pruning sparse matrix multiplication sparse tensor cores

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FPGA-Based sparse matrix multiplication Accelerators: From State-of-the-Art to Future Opportunities

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ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS 2024年第4期17卷 1-37页

作者： Liu, Yajing Chen, Ruiqi Li, Shuyang Yang, Jing Li, Shun DA Silva, Bruno Fuzhou Univ Fuzhou Peoples R China Vrije Univ Brussel Brussels Belgium Fudan Univ Shanghai Peoples R China VeriMake Innovat Lab Nanjing Peoples R China

sparse matrix multiplication (SpMM) plays a critical role in high-performance computing applications, such as deep learning, image processing, and physical simulation. Field-Programmable Gate Arrays (FPGAs), with their configurable hardware resources, can be tailored to accelerate SpMMs. There has been considerable research on deploying sparse matrix multipliers across various FPGA platforms. However, the FPGA-based design of sparse matrix multipliers still presents numerous challenges. Therefore, it is necessary to summarize and organize the current work to provide a reference for further research. This article first introduces the computational method of SpMM and categorizes the different challenges of FPGA deployment. Following this, we introduce and analyze a variety of state-of-the-art FPGA-based accelerators tailored for SpMMs. In addition, a comparative analysis of these accelerators is performed, examining metrics including compression rate, throughput, and resource utilization. Finally, we propose potential research directions and challenges for further study of FPGA-based SpMM accelerators.

关键词： Field-Programmable Gate Array (FPGA) sparse matrix multiplication Compress Ratio Accelerator

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S-MPEC: sparse matrix multiplication Performance Estimator on a Cloud Environment

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CLUSTER COMPUTING-THE JOURNAL OF NETWORKS SOFTWARE TOOLS AND APPLICATIONS 2023年第5期26卷 2563-2576页

作者： Park, Jueon Lee, Kyungyong Kookmin Univ Dept Comp Sci Seoul South Korea

sparse matrix multiplication (SPMM) is widely used for various machine learning algorithms. As the applications of SPMM using large-scale datasets become prevalent, executing SPMM jobs on an optimized setup has become very important. Execution environments of distributed SPMM tasks on cloud resources can be set up in diverse ways with respect to the input sparse datasets, distinct SPMM implementation methods, and the choice of cloud instance types. In this paper, we propose S-MPEC which can predict latency to complete various SPMM tasks using Apache Spark on distributed cloud environments. We first characterize various distributed SPMM implementations on Apache Spark. Considering the characters and hardware specifications on the cloud, we propose unique features to build a GB-regressor model and Bayesian optimizations. Our proposed S-MPEC model can predict latency on an arbitrary SPMM task accurately and recommend an optimal implementation method. Thorough evaluation of the proposed system reveals that a user can expect 44% less latency to complete SPMM tasks compared with the native SPMM implementations in Apache Spark.

关键词： Cloud computing Instance recommendation sparse matrix multiplication Apache Spark

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Sparm: A sparse matrix multiplication Accelerator Supporting Multiple Dataflows 35

Sparm: A Sparse Matrix Multiplication Accelerator Supporting...

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35th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP)

作者： Luo, Shengbai Wang, Bo Shi, Yihao Zhang, Xueyi Xue, Qingshan Ma, Sheng Natl Univ Def Technol Changsha Peoples R China

ISBN: (纸本)9798350349641;9798350349634

As the main workload of many scientific and machine learning applications, sparse matrix-matrix multiplication (spGEMM) has become a hot research field. The current spGEMM workloads exhibit sparsity and irregularity, leading to computational inefficiencies on traditional hardware platforms and motivating numerous customized accelerators. These specialized hardware designs typically accelerate only one type of spGEMM dataflow (such as Inner-Product, Outer-Product, or Gustavson), yet the computational efficiency of the same spGEMM kernel can vary significantly under different dataflows. Flexagon is the first spGEMM accelerator to support multiple dataflows, but its MRN (Merger-Reduction Network) design causes a lot of data blocking and load imbalance, which limits its performance. In this work, we propose Sparm, which achieves efficient merging of psums (partial sums) for different dataflows through a specialized indexing unit. Sparm addresses the performance bottlenecks encountered by Flexagon when facing highly sparse matrices. Furthermore, Sparm employs a row/column prefetcher to load the streaming matrices proactively and thus significantly reduces the amount of DRAM access. We conduct simulations using a cycle-accurate simulator on workloads from various application domains, and the results demonstrate that Sparm achieves average performance gains of 2.62x and 1.35x compared to state-of-the-art spGEMM accelerators SIGMA and Flexagon. Meanwhile, Sparm brings only a small amount of additional hardware overhead over Flexagon.

关键词： sparse matrix multiplication Domain-Specific accelerator Dataflow Data Reuse

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Row-Wise Product-Based sparse matrix multiplication Hardware Accelerator With Optimal Load Balancing

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IEEE ACCESS 2022年 10卷 64547-64559页

作者： Lee, Jong Hun Park, Beomjin Kong, Joonho Munir, Arslan LX Semicon Seoul 06763 South Korea Samsung Elect Hwaseong 18448 South Korea Kyungpook Natl Univ Sch Elect & Elect Engn Daegu 41566 South Korea Kyungpook Natl Univ Sch Elect Engn Daegu 41566 South Korea Kansas State Univ Dept Comp Sci Manhattan KS 66506 USA

matrix multiplication is a main computation kernel of emerging workloads, such as deep neural networks and graph analytics. These workloads often exhibit high sparsity in data, which means a large portion of the elements in the data are zero-valued elements. Though systolic arrays have shown a significant performance and energy efficiency improvement over central processing units (CPUs) or graphic processing units (GPUs) when executing matrix multiplications, data sparsity is largely overlooked in the conventional systolic arrays. In this paper, we propose a row-wise product-based sparse matrix multiplication (SpMM) hardware accelerator for compressed sparse row (CSR)-formatted input matrices. Our hardware accelerator leverages row-wise product, which has advantages over inner-product or outer-product when executing the sparse matrix multiplications. As compared to the conventional systolic arrays, which cannot skip the ineffectual operations, our hardware accelerator only performs effectual operations with non-zero elements, improving the performance when executing SpMM. In addition, we also propose an optimal load balancing scheme when using multiple processing elements (PEs). Our load balancing scheme utilizes an operation count-based matrix tiling for parallel execution of the PEs and resource contention avoidance. According to our evaluation, our 32PE-SpMM accelerator shows 13.6x -47.9x speedup over tensor processing unit (TPU)-like systolic arrays, on average. Furthermore, our operation count-based load balancing scheme shows better performance over the fixed tiling and non-zero element count-based tiling by up to 8.48% and 6.28%, respectively, with only up to 0.06% matrix tiling pre-processing latency overhead.

关键词： sparse matrix multiplication row-wise product load balancing matrix tiling speedup

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HARP: Hardware-Based Pseudo-Tiling for sparse matrix multiplication Accelerator 23

HARP: Hardware-Based Pseudo-Tiling for Sparse Matrix Multipl...

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56th IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Kim, Jinkwon Jang, Myeongjae Nam, Haejin Kim, Soontae Korea Adv Inst Sci & Technol Daejeon South Korea

ISBN: (纸本)9798400703294

General sparse matrix-matrix multiplication (SpGEMM) is a memory-bound workload, due to the compression format used. To minimize data movements for input matrices, outer product accelerators have been proposed. Since these accelerators access input matrices only once and then generate numerous partial products, managing the generated partial products is the key optimization factor. To reduce the number of partial products handled, the state-of-the-art accelerator uses software to tile an input matrix. However, the software-based tiling has three limitations. First, a user manually executes the tiling software and manages the tiles. Second, generating a compression format for each tile incurs memory-intensive operations. Third, an accelerator that uses the compression format cannot skip ineffectual accesses for input matrices. To overcome these limitations, this paper proposes hardware-based pseudo-tiling (HARP), which enables logical tiling of the original compressed matrix without generating a compression format for each tile. To this end, HARP utilizes our proposed Run-time Operand Descriptor to point to an effectual column-row pair in a pseudo-tile. Consequently, HARP enables a user to use the accelerator as a normal SpGEMM operation does without tiling. Furthermore, HARP does not require a compression format for each tile and can skip ineffectual accesses for input matrices. To further improve the efficiency of pseudo-tiling, HARP performs super-tiling to combine pseudo-tiles and sub-tiling to further tile a pseudo-tile. Experiment results show that HARP achieves 4x, 35x, and 33x speedup and 5x, 664x, and 233x energy efficiency on average compared to the state-of-the-art outer product accelerator, CPU (MKL), and GPU (cusparse), respectively.

关键词： sparse matrix sparse matrix multiplication SpGEMM Spare matrix tiling Tiling Hardware accelerator Application-specific hardware

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EMBARK: Memory bounded architectural improvement in CSR-CSC sparse matrix multiplication 9

EMBARK: Memory bounded architectural improvement in CSR-CSC ...

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IEEE 9th International Conference on Collaboration and Internet Computing (CIC)

作者： Jayakody, Shakya Wang, Jun Univ Cent Florida Dept Elect & Comp Engn Orlando FL 32816 USA

ISBN: (纸本)9798350339123

sparse matrix multiplication (SpMM) is a crucial algorithm in modern platforms such as Artificial Intelligence (AI), Graph Neural Network (GNN), Graph Convolutional Network (GCN), and neural network image processing. However, the performance of SpMM is limited by several factors, such as memory storage, data reuse, I/O traffic, and memory access. To address these challenges, we have developed a dynamic memory allocation method called EMBARK, specifically including a new Compressed sparse Row (CSR) x Compressed sparse Column (CSC) matrix multiplication algorithm that reduces significant matrix decompression/compression overhead and optimizes storage allocation. Our CSRxCSC algorithm is based on memory partitioning techniques: EMBARK, values, and rowid are together, and colptr is stored separately in the main memory. To improve the performance of our algorithm, the main memory is utilized to store hot data for values, colid, and rowid, while the Non-volatile Memory (NVM) stores partial hot data based on a rank-based page replacement strategy. We have conducted experiments with Suitesparse matrix real datasets, and our results show CSRxCSC-EMBARK reduced the execution time average by 46.44% compared to the baseline matrix-by-matrix multiplication (MxM).

关键词： sparse matrix multiplication Compressed sparse Row Compressed sparse Column Non-volatile Memory Memory Allocation

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SPADA: Accelerating sparse matrix multiplication with Adaptive Dataflow 2023

SPADA: Accelerating Sparse Matrix Multiplication with Adapti...

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28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)

作者： Li, Zhiyao Li, Jiaxiang Chen, Taijie Niu, Dimin Zheng, Hongzhong Xie, Yuan Gao, Mingyu Tsinghua Univ Beijing Peoples R China Northwestern Univ Evanston IL 60208 USA Alibaba DAMO Acad Hangzhou Peoples R China Shanghai Qi Zhi Inst Shanghai Peoples R China

ISBN: (纸本)9781450399166

sparse matrix-matrix multiplication (SpGEMM) is widely used in many scientific and deep learning applications. The highly irregular structures of SpGEMM limit its performance and efficiency on conventional computation platforms, and thus motivate a large body of specialized hardware designs. Existing SpGEMM accelerators only support specific types of rigid execution dataflow such as inner/output-product or row-based schemes. Each dataflow is only optimized for certain sparse patterns and fails to generalize with robust performance to the widely diverse SpGEMM workloads across various domains. We propose Spada, a combination of three novel techniques for SpGEMM accelerators to efficiently adapt to various sparse patterns. First, we describe a window-based adaptive dataflow that can be flexibly adapted to different modes to best match the data distributions and realize different reuse benefits. Then, our hardware architecture efficiently supports this dataflow template, with flexible, fast, and low-cost reconfigurability and effective load balancing features. Finally, we use a profiling-guided approach to detect the sparse pattern and determine the optimized dataflow mode to use, based on the key observations of sparse pattern similarity in nearby matrix regions. Our evaluation results demonstrate that Spada is able to match or exceed the best among three state-of-the-art SpGEMM accelerators, and avoid the performance degradation of the others if data distribution and dataflow mismatch. It achieves an average 1.44x speedup across a wide range of sparse matrices and compressed neural network models.

关键词： sparse matrix multiplication hardware acceleration dataflow

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